PDF MSM514221B Data sheet ( Hoja de datos )

Número de pieza	MSM514221B
Descripción	DRAM / FAST PAGE MODE TYPE
Fabricantes	OKI electronic componets
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No Preview Available ! E2L0029-17-Y1 ¡¡SemicondSucetormiconductor MSM514221B 262,263-Word ¥ 4-Bit Field Memory This versioMnS: MJa5n1. 41299281B Previous version: Dec. 1996 DESCRIRTION The OKI MSM514221B is a high performance 1-Mbit, 256K ¥ 4-bit, Field Memory. It is designed for high-speed serial access applications such as HDTVs, conventional NTSC TVs, VTRs, digital movies and Multi-media systems. It is a FRAM for wide or low end use as general commodity TVs and VTRs, exclusively. The MSM514221B is not designed for the other use or high end use in medical systems, professional graphics systems which require long term picture, and data storage systems and others. The 1-Mbit capacity fits one field of a conventional NTSC TV screen. Each of the 4-bit planes has separate serial write and read ports. These employ independent control clocks to support asynchronous read and write operations. Different clock rates are also supported that allow alternate data rates between write and read data streams. The MSM514221B provides high speed FIFO, First-In First-Out, operation without external refreshing: it refreshes its DRAM storage cells automatically, so that it appears fully static to the users. Moreover, fully static type memory cells and decoders for serial access enable refresh free serial access operation, so that the serial read and/or write control clock can be halted high or low for any duration as long as the power is on. Internal conflicts of memory access and refreshing operations are prevented by special arbitration logic. The MSM514221B's function is simple, and similar to a digital delay device whose delay-bit- length is easily set by reset timing. The delay length, number of read delay clocks between write and read, is determined by externally controlled write and read reset timings. Additional SRAM serial registers, or line buffers for the initial access of 256 ¥ 4-bit enable high speed first-bit-access with no clock delay just after the write or read reset timings. The MSM514221B is similar in operation and functionality to OKI 2-Mbit Field Memory MSM518221. 1/15 1 page ¡ Semiconductor MSM514221B OPERATION Write Operation The write operation is controlled by three clocks, SWCK, RSTW, and WE. Write operation is accomplished by cycling SWCK, and holding WE high after the write address pointer reset operation or RSTW. Each write operation, which begins after RSTW, must contain at least 130 active write cycles, i.e. SWCK cycles while WE is high. To transfer the last data to the DRAM array, which at that time is stored in the serial data registers attached to the DRAM array, an RSTW operation is required after the last SWCK cycle. Write Reset : RSTW The first positive transition of SWCK after RSTW becomes high resets the write address counters to zero. RSTW setup and hold times are referenced to the rising edge of SWCK. Because the write reset function is solely controlled by the SWCK rising edge after the high level of RSTW, the states of WE are ignored in the write reset cycle. Before RSTW may be brought high again for a further reset operation, it must be low for at least two SWCK cycles. Data Inputs : DIN0 - 3 Write Clock : SWCK The SWCK latches the input data on chip when WE is high, and also increments the internal write address pointer. Data-in setup time tDS, and hold time tDH are referenced to the rising edge of SWCK. Write Enable : WE WE is used for data write enable/disable control. WE high level enables the input, and WE low level disables the input and holds the internal write address pointer. There are no WE disable time (low) and WE enable time (high) restrictions, because the MSM514221B is in fully static operation as long as the power is on. Note that WE setup and hold times are referenced to the rising edge of SWCK. 5/15 5 Page ¡ Semiconductor MSM514221B TIMING WAVEFORM Write Cycle Timing (Write Reset) n Cycle 0 Cycle 1 Cycle 2 Cycle – VIH SWCK – VIL RSTW tT tDS tRSTWS tDH DIN n tRSTWH 0 WE tWSWH tWSWL tSWC 12 3 – VIH – VIL – VIH – VIL – VIH – VIL Write Cycle Timing (Write Enable) SWCK WE ,,,DIN n Cycle Disable Cycle Disable Cycle n + 1 Cycle tWENH tWDSH tWDSS tWWEL n tWWEH tWENS n+ 1 n+2 – VIH – VIL – VIH – VIL – VIH – VIL RSTW – VIH – VIL 11/15 11 Page

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