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PDF IBM25PPC440GX Data sheet ( Hoja de datos )
| Número de pieza | IBM25PPC440GX | |
| Descripción | PowerPC 440GX Embedded Processor | |
| Fabricantes | IBM Microelectronics | |
| Logotipo |  |
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PowerPC 440GX Embedded Processor Data Sheet
Preliminary
Features
• PowerPC® 440 processor core operating up to
800MHz with 32KB I- and D-caches (with parity
checking)
• On-chip 256KB SRAM configurable as L2 Code
store or Ethernet Packet store memory
• Selectable processor:bus clock ratios (Refer to
the Clocking chapter in the PPC440GX
Embedded Processor User’s Manual for details)
• Double Data Rate (DDR) Synchronous DRAM
(SDRAM) interface operating up to 166MHz
• External Peripheral Bus (32 bits) for up to eight
devices with external mastering
• DMA support for external peripherals, internal
UART and memory
• PCI-X V1.0a interface (32 or 64 bits, up to
133MHz) with support for conventional PCI
V2.3
• Two Ethernet 10/100/1000Mbps half- or full-
duplex interfaces. Operational modes
supported are SMII, GMII, RGMII, TBI and
RTBI.
• TCP/IP Acceleration Hardware (TAH) provided
for 10/100/1000 Mbps ports that performs
checksum processing, TCP segmentation, and
includes support for jumbo frames
• Two Ethernet 10/100Mbps half- or full-duplex
interfaces. Operational modes supported are
MII, RMII, and SMII.
• Programmable Interrupt Controller supports
interrupts from a variety of sources.
• I2O Messaging unit for message transfer
between the CPU and PCI-X
• Programmable General Purpose Timers (GPT)
• Two serial ports (16750 compatible UART)
• Two IIC interfaces
• General Purpose I/O (GPIO) interface available
• JTAG interface for board level testing
• Processor can boot from PCI memory
Description
Designed specifically to address high-end
embedded applications, the PowerPC 440GX
(PPC440GX) provides a high-performance, low
power solution that interfaces to a wide range of
peripherals by incorporating on-chip power
management features and lower power dissipation.
This chip contains a high-performance RISC
processor core, DDR SDRAM controller,
configurable 256KB SRAM to be used as L2 cache
or software-controlled on-chip memory, PCI-X bus
interface, Gigabit Ethernet interfaces, TCP/IP
acceleration hardware, I2O messaging unit, control
for external ROM and peripherals, DMA with
scatter-gather support, serial ports, IIC interface,
and general purpose I/O.
Technology: IBM CMOS Cu-11, 0.13µm , 6-layer
metal
Package: 25mm, 552-ball Ceramic Ball Grid Array
(CBGA)
Power (estimated): Less than:
4W @533MHz
5W @667MHz
6W @800MHz
Supply voltages required: 3.3V, 2.5V, 1.5V
2/12/04
While the information contained herein is believed to be accurate, such information is preliminary, and should not be
relied upon for accuracy or completeness, and no representations or warranties of accuracy or completeness are made.
Page 1 of 74
1 page  
PowerPC 440GX Embedded Processor Data Sheet
PPC440GX Functional Block Diagram
Preliminary
Universal
Interrupt
Controller
Clock
Control
Reset
Power
Mgmt
Timers
MMU
DCRs
63 internal
18 external
PPC440
Processor Core
DCR Bus
GP
Timers
GPIO
IIC
x2
UART
x2
JTAG
32 KB
D-Cache
Trace
32 KB
I-Cache
L2 Controller
Arb On-chip Peripheral Bus (OPB)
SRAM
256 KB
DMA
Controller
(4-Channel)
OPB
Bridge
Processor Local Bus (PLB)
I2O
Messaging
PCI-X
Bridge
MAL
DDR SDRAM
Controller
TAH
10/100
10/100/ x2
1000 x2
Ethernet
RGMII ZMII
Bridge Bridge
External External
Bus Master Bus
Controller Controller
83MHz max
32-bit addr
32-bit data
133MHz max 166MHz max
13-bit addr
32/64-bit data
1 GMII
or
2 RGMII
or
1 TBI
or
2 RTBI
1 MII
or
2 RMII
or
4 SMII
The PPC440GX is designed using the IBM Microelectronics Blue Logic™ methodology in which major
functional blocks are integrated together to create an application-specific product (ASIC). This approach
provides a consistent way to create complex ASICs using IBM CoreConnect Bus™ Architecture.
Note: IBM CoreConnect buses provide:
• 128-bit PLB interfaces up to 166.66MHz, 2.6GB/s on both the Read and Write data path (5.2GB/s
total)
• 32-bit OPB interfaces up to 83.33MHz, 333MB/s
Address Maps
The PPC440GX incorporates two address maps. The first is a fixed processor system memory address map.
This address map defines the possible contents of various address regions which the processor can access.
The second address map is for Device Configuration Registers (DCRs). The DCRs are accessed by software
running on the PPC440GX processor through the use of mtdcr and mfdcr instructions.
2/12/04
Page 5 of 74
5 Page 
Preliminary
PowerPC 440GX Embedded Processor Data Sheet
• External master interface
– Write posting from external master
– Read prefetching on PLB for external master reads
– Bursting capable from external master
– Allows external master access to all non-EBC PLB slaves
– External master can control EBC slaves for own access and control
Ethernet Controller Interface
Ethernet support provided by the PPC440GX interfaces to the physical layer, but the PHY is not included on
the chip.
Features include:
• One to four 10/100 interfaces running in full- and half-duplex modes
– One full Media Independent Interface (MII) with 4-bit parallel data transfer
– Two Reduced Media Independent Interfaces (RMII) with 2-bit parallel data transfer
– Four Serial Media Independent Interfaces (SMII)
• One or two GMII interfaces running in full- and half-duplex modes at 10Mb/s or 100Mb/s or 1000Mb/s
– One full Gigabit Media Independent Interface (GMII) with 8-bit parallel data transfer
– Two Reduced Gigabit Media Independent Interfaces (RGMII) with 4-bit parallel data transfer
• One or two TBI interfaces running in full- and half-duplex modes at 10Mb/s or 100Mb/s or 1000Mb/s
– One full Ten Bit Interface (TBI) with 10-bit parallel data transfer
– Two Reduced Ten Bit Interfaces (RTBI) with 4-bit parallel data transfer
• Jumbo frame support (9016 byte)
– Support for Ethernet II formatted frames (RFC894)
– Support for IEEE formatted frames (RFC1042)
– Handles VLAN-tagged frames
TCP/IP Acceleration Hardware (TAH)
Features include:
• Offloads Gigabit Ethernet protocol processing from the CPU
• Checksum verification for TCP/UDP/IP headers in the receive path
• Checksum generation for TCP/UDP/IP headers in the transmit path
• TCP segmentation support in the transmit path
DMA Controller
Features include:
• Supports the following transfers:
– Memory-to-memory transfers
– Buffered peripheral to memory transfers
– Buffered memory to peripheral transfers
• Four channels
• Scatter/Gather capability for programming multiple DMA operations
• 8-, 16-, 32-bit peripheral support (OPB and external)
• 64-bit addressing
• 128 byte FIFO buffer
• Address increment or decrement
• Supports internal and external peripherals
• Support for memory mapped peripherals
• Support for peripherals running on slower frequency buses
2/12/04
Page 11 of 74
11 Page | ||
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| PDF Descargar | [ Datasheet IBM25PPC440GX.PDF ] | |
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