PDF MC74HC573A Data sheet ( Hoja de datos )

Número de pieza	MC74HC573A
Descripción	Octal 3-State Inverting Transparent Latch
Fabricantes	Motorola Semiconductors
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No Preview Available ! MOTOROLA SEMICONDUCTOR TECHNICAL DATA Octal 3-State Noninverting Transparent Latch High–Performance Silicon–Gate CMOS The MC54/74HC573A is identical in pinout to the LS573. The devices are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. These latches appear transparent to data (i.e., the outputs change asynchronously) when Latch Enable is high. When Latch Enable goes low, data meeting the setup and hold time becomes latched. The HC573A is identical in function to the HCT373A but has the data inputs on the opposite side of the package from the outputs to facilitate PC board layout. The HC573A is the noninverting version of the HC563A. • Output Drive Capability: 15 LSTTL Loads • Outputs Directly Interface to CMOS, NMOS and TTL • Operating Voltage Range: 2.0 to 6.0 V • Low Input Current: 1.0 µA • In Compliance with the Requirements Defined by JEDEC Standard No. 7A • Chip Complexity: 218 FETs or 54.5 Equivalent Gates LOGIC DIAGRAM DATA INPUTS D0 2 D1 3 D2 4 D3 5 D4 6 D5 7 D6 8 D7 9 LATCH ENABLE 11 OUTPUT ENABLE 1 19 Q0 18 Q1 17 Q2 16 Q3 15 Q4 14 Q5 13 Q6 12 Q7 NONINVERTING OUTPUTS PIN 20 = VCC PIN 10 = GND ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎDesign Criteria ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInternal Gate Count* ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInternal Gate Propagation Delay ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInternal Gate Power Dissipation ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSpeed Power Product Value Units 54.5 ea. 1.5 ns 5.0 µW 0.0075 pJ * Equivalent to a two–input NAND gate. MC54/74HC573A 20 1 20 1 20 1 J SUFFIX CERAMIC PACKAGE CASE 732–03 N SUFFIX PLASTIC PACKAGE CASE 738–03 DW SUFFIX SOIC PACKAGE CASE 751D–04 20 1 DT SUFFIX TSSOP PACKAGE CASE 948E–02 ORDERING INFORMATION MC54HCXXXAJ MC74HCXXXAN MC74HCXXXADW MC74HCXXXADT Ceramic Plastic SOIC TSSOP PIN ASSIGNMENT OUTPUT ENABLE D0 1 2 20 VCC 19 Q0 D1 3 18 Q1 D2 4 17 Q2 D3 5 16 Q3 D4 6 15 Q4 D5 7 14 Q5 D6 8 13 Q6 D7 9 GND 10 12 Q7 11 LATCH ENABLE FUNCTION TABLE Inputs Output Output Latch Enable Enable D Q L HH H L HL L L L X No Change H XX Z X = Don’t Care Z = High Impedance 10/96 © Motorola, Inc. 1996 1 REV 7 1 page MC54/74HC573A SWITCHING WAVEFORMS tr INPUT D tPLH Q 90% 50% 10% 90% 50% 10% tTLH Figure 1. tf VCC GND tPHL tTHL LATCH ENABLE 50% tw tPLH tPHL Q 50% Figure 2. VCC GND OUTPUT ENABLE Q Q 50% tPZL tPLZ 50% tPZH tPHZ 1.3 V Figure 3. 3.0 V GND HIGH IMPEDANCE 10% VOL 90% VOH HIGH IMPEDANCE INPUT D LATCH ENABLE VALID 50% tSU th 50% Figure 4. VCC GND VCC GND DEVICE UNDER TEST TEST POINT OUTPUT CL* * Includes all probe and jig capacitance Figure 5. Test Circuit DEVICE UNDER TEST TEST POINT OUTPUT 1 kΩ CL* CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ AND tPZH. * Includes all probe and jig capacitance Figure 6. Test Circuit D0 2 D1 3 D2 4 D3 5 D4 6 D5 7 D6 8 D7 9 EXPANDED LOGIC DIAGRAM D Q LE D Q LE D Q LE D Q LE D Q LE D Q LE D Q LE D Q LE 19 Q0 18 Q1 17 Q2 16 Q3 15 Q4 14 Q5 13 Q6 12 Q7 LATCH ENABLE 11 OUTPUT ENABLE 1 High–Speed CMOS Logic Data DL129 — Rev 6 5 MOTOROLA 5 Page

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