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PDF MSM7704 Data sheet ( Hoja de datos )
| Número de pieza | MSM7704 | |
| Descripción | 2ch Single Rail CODEC | |
| Fabricantes | OKI electronic componets | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de MSM7704 (archivo pdf) en la parte inferior de esta página. Total 17 Páginas | ||
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E2U0021-28-81
¡¡SemicondSucetormiconductor
MSM7704-01/02/03
2ch Single Rail CODEC
This vMerSsMio7n7: 0A4u-0g1. /10929/803
Previous version: Nov. 1996
GENERAL DESCRIPTION
The MSM7704-01/7704-02/7704-03 are two-channel CODEC CMOS ICs for voice signals ranging
from 300 to 3400 Hz. These devices contain filters for A/D and D/A conversion.
Designed especially for a single-power supply and low-power applications, these devices
contain two-channel AD/DA converters in a single chip and achieve a reduced footprint and a
reduced number of external components.
The MSM7704-01/7704-02/7704-03 are best suited for an analog interface to an echo canceller
DSP used in digital telephone terminals, digital PABXs, and hands free terminals.
FEATURES
• Single power supply: +2.7 V to +3.8 V
• Power consumption
Operating mode:
30 mW Typ.
50 mW Max.
Power-saving mode:
3 mW Typ.
6 mW Max.
Power-down mode: 0.03 mW Typ. 0.3 mW Max.
• ITU-T Companding law
MSM7704-01: m/A-law pin-selectable
MSM7704-02: m-law
MSM7704-03: A-law
• Built-in PLL eliminates a master clock
• The PCM interface can be switched between 2 channel serial/parallel
• Transmission clock: 64/128/256/512/1024/2048 kHz
96/192/384/768/1536/1544/200 kHz
(During 2 channel serial mode, the 64 and 96 kHz clocks are disabled)
• Adjustable transmit gain
• Built-in reference voltage supply
• Analog output can directly drive a 1.2 kW load
• Package:
24-pin plastic SOP (SOP24-P-430-1.27-K) (Product name : MSM7704-01GS-K)
(Product name : MSM7704-02GS-K)
(Product name : MSM7704-03GS-K)
1/17
1 page  
¡ Semiconductor
MSM7704-01/02/03
DIN1
PCM signal input for channel 1 when the parallel mode is selected.
D/A conversion is performed with the serial PCM signal input to this pin, the RSYNC signal
synchronous with the serial PCM signal, and the BCLK signal, and then the analog output is
output from AOUT1 pin.
The data rate of the PCM signal is equal to the frequency of the BCLK signal.
The PCM signal is shifted at the falling edge of the BCLK signal and latched into the internal
register when shifted by eight bits.
The start of the PCM data (MSD) is identified at the rising edge of RSYNC.
When the serial mode is selected, this pin is not used and should be connected to GND (0 V).
DIN2
PCM signal input for channel 2 when the parallel mode is selected.
D/A conversion is performed with the serial PCM signal input to this pin, the RSYNC signal
synchronous with the serial PCM signal, and the BCLK signal, and then the analog output is
output from AOUT2 pin.
The data rate of the PCM signal is equal to the frequency of the BCLK signal.
The PCM signal is shifted at the falling edge of the BCLK signal and latched into the internal
register when shifted by eight bits.
The start of the PCM data (MSD) is identified at the rising edge of RSYNC.
When the serial mode is selected, this pin is used for the 2ch multiplexed PCM signal input.
BCLK
Shift clock signal input for the DIN1, DIN2, DOUT1, and DOUT2 signals.
The frequency, equal to the data rate, is 64, 96, 128, 192, 256, 384, 512, 768, 1024, 1536, 1544, 2048,
or 200 kHz. Setting this signal to logic "1" or "0" drives both transmit and receive circuits to the
power saving state.
RSYNC
Receive synchronizing signal input.
Eight bits PCM data required are selected from a series of PCM signal to the DIN1 and DIN2 pins
by the receive synchronizing signal.
All timing signals in the receive section are synchronized by this synchronizing signal. This
signal must be synchronized in phase with the BCLK (generated from the same clock source as
BCLK). The frequency should be 8 kHz ±50 ppm to guarantee the AC characteristics which are
mainly the frequency characteristics of the receive section.
However, unless the frequency characteristics of the system used are strictly specified, this
device can operate in the range of 6 kHz to 9 kHz, but the electrical characteristics specified in
the data sheet are not guaranteed.
5/17
5 Page 
¡ Semiconductor
MSM7704-01/02/03
AC Characteristics
(VDD = 2.7 V to 3.8 V, Ta = –30°C to +85°C)
Parameter
Symbol
Loss T1
Loss T2
Transmit Frequency Response
Loss T3
Loss T4
Loss T5
Loss T6
Loss R1
Loss R2
Receive Frequency Response
Loss R3
Loss R4
Loss R5
SD T1
SD T2
Transmit Signal to Distortion Ratio SD T3
SD T4
SD T5
SD R1
SD R2
Receive Signal to Distortion Ratio SD R3
SD R4
SD R5
GT T1
GT T2
Transmit Gain Tracking
GT T3
GT T4
GT T5
GT R1
GT R2
Receive Gain Tracking
GT R3
GT R4
Freq.
(Hz)
60
300
1020
2020
3000
3400
300
1020
2020
3000
3400
1020
1020
1020
1020
GT R5
Level Condition
(dBm0)
0
0
3
0
–30
–40 *1
–45
3
0
–30
–40 *1
–45
3
–10
–40
–50
–55
3
–10
–40
–50 *2
–55 *2
Min.
20
–0.15
–0.15
–0.15
0
–0.15
–0.15
–0.15
0.0
35
35
35
28
23
36
36
36
30
25
–0.3
–0.3
–0.5
–1.2
–0.3
–0.4
–1.0
–1.2
Typ.
26
+0.07
Reference
–0.04
+0.06
0.4
–0.03
Reference
+0.02
+0.12
0.46
43
41
38
31.5
27
43
41
40
33.5
30
+0.01
Reference
0
–0.03
–0.05
–0.06
Reference
+0.2
+0.62
+0.20
+0.65
+0.3
Max.
—
+0.20
+0.20
+0.20
0.80
+0.20
+0.20
+0.20
0.80
—
—
—
—
—
—
—
—
—
—
+0.3
+0.3
+0.5
+1.2
+0.3
+0.4
+1.0
+1.2
Unit
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
*1 Psophometric filter is used
*2 Upper is specified for the m-law, lower for the A-law
11/17
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet MSM7704.PDF ] | |
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