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PDF MSM7717 Data sheet ( Hoja de datos )
| Número de pieza | MSM7717 | |
| Descripción | Single Rail CODEC | |
| Fabricantes | OKI electronic componets | |
| Logotipo |  |
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E2U0041-28-81
¡¡SemicondSucetormiconductor
MSM7717-01/02/03
Single Rail CODEC
This vMerSsMio7n7: 1A7u-0g1. /10929/803
Previous version: Nov. 1996
GENERAL DESCRIPTION
The MSM7717 is a single-channel CODEC CMOS IC for voice signals ranging from 300 to 3400
Hz with filters for A/D and D/A conversion.
Designed especially for a single-power supply and low-power applications, the device is
optimized for ISDN terminals and telephone terminals in digital wireless systems.
The device uses the same transmission clocks as those used in the MSM7508B and MSM7509B.
The analog output, which can drive a 1.2 kW load, can directly drive a handset receiver
differentially.
FEATURES
• Single power supply: 2.7 V to 3.8 V
• Low power consumption
Operating mode:
20 mW Typ. VDD = 3 V
Power-down mode: 0.03 mW Typ. VDD = 3 V
• Conforms to ITU-T Companding law
MSM7717-01: m/A-law pin selectable
MSM7717-02: m-law
MSM7717-03: A-law
• Built-in PLL eliminates a master clock
• Serial data rate: 64/128/256/512/1024 kHz
96/192/384/768/1536/1544/2048/200 kHz
• Adjustable transmit gain
• Adjustable receive gain
• Built-in reference voltage supply
• Package options:
24-pin plastic SOP (SOP24-P-430-1.27-K) (Product name: MSM7717-01GS-K)
(Product name: MSM7717-02GS-K)
(Product name: MSM7717-03GS-K)
20-pin plastic SSOP (SSOP20-P-250-0.95-K) (Product name: MSM7717-01MS-K)
(Product name: MSM7717-02MS-K)
(Product name: MSM7717-03MS-K)
1/19
1 page  
¡ Semiconductor
MSM7717-01/02/03
PWI, AOUT+, AOUT–
PWI is connected to the inverting input of the receive driver.
The receive driver output is connected to the AOUT– pin. Therefore, the receive level can be
adjusted with the pins VFRO, PWI, and AOUT–. When the PWI pin is not used, the PWI pin to
the AOUT– pin, and leave the pins AOUT– and AOUT+ open. The output of AOUT+ is inverted
with respect to the output of AOUT–. Since these outputs provide differential drive of an
impedance of 1.2 kW, these outputs can directly be connected to a receiver of handset using a
piezoelectric earphone. Refer to the application example. Since the driver amplifiers are being
activated during the power-saving mode, the amplifiers can output other external signals from
AOUT+ and AOUT– pins. AOUT+ and AOUT– outputs are in a high impedance state during
the power-down mode.
External Signal Input
VI
Receive filter
–
SG +
VFRO
PWI
AOUT–
R6
R7
Analog output
–
SG +
VO ZL ZL > 1.2 kW
AOUT+
Analog inverted output
R6 > 20 kW
Gain = VO/VI = R7/R6 £ 1
VDD
Power supply for 2.7 V to 3.8 V. (Typically 3.0 V)
PCMIN
PCM data input.
A serial PCM data input to this pin is converted to an analog signal in synchronization with the
RSYNC signal and BCLK signal.
The data rate of PCM is equal to the frequency of the BCLK signal.
PCM signal is shifted in at a falling edge of the BCLK signal and latched into the internal register
when shifted by eight bits.
The start of the PCM data (MSD) is identified at the rising edge of RSYNC.
BCLK
Shift clock signal input for the PCMIN and PCMOUT signal.
The frequency, equal to the data rate, is 64, 96, 128, 192, 256, 384, 512, 768, 1024, 1536, 1544, or 2048
kHz. Setting this signal to logic "1" or "0" drives both transmit and receive circuits to the power
saving state.
The power-saving state means that the reference voltage generator (VRGEN), PLL, and receive
driver amplifiers are in the operating mode and the other circuits are in the non-operating mode.
5/19
5 Page 
¡ Semiconductor
MSM7717-01/02/03
Transmit Analog Interface Characteristics
(VDD = 2.7 V to 3.8 V, Ta = –30°C to +85°C)
Parameter
Symbol
Condition
Min. Typ. Max. Unit
Input Resistance
RINX AIN+, AIN–
10 — — MW
Output Load Resistance
RLGX GSX with respect to SG
20 — — kW
Output Load Capacitance
CLGX
— — 30 pF
Output Amplitude
VOGX
–0.7 — +0.7 V
Offset Voltage
VOSGX
Gain = 1
–20 — +20 mV
Receive Analog Interface Characteristics
(VDD = 2.7 V to 3.8 V, Ta = –30°C to +85°C)
Parameter
Symbol
Condition
Min. Typ. Max. Unit
Input Resistance
RINPW PWI
RLVF VFRO with respect to SG
10 — — MW
20 — — kW
Output Load Resistance
AOUT+, AOUT– (each) with
RLAO respect to SG
0.6 — — kW
Output Load Capacitance
Output Amplitude
CLVF VFRO
— — 30 pF
CLAO AOUT+, AOUT–
— — 50 pF
VOVF
VFRO, RL = 20 kW with
respect to SG
–1.0 — +1.0 V
VOAO
AOUT+, AOUT–, RL = 0.6 kW
with respect to SG
–1.0
—
+1.0 V
VOSVF VFRO with respect to SG
–100 — +100 mV
Offset Voltage
AOUT+, AOUT–, Gain = 1 with
VOSAO respect to SG
–100 — +100 mV
11/19
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet MSM7717.PDF ] | |
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