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PDF MSM7731-01 Data sheet ( Hoja de datos )
| Número de pieza | MSM7731-01 | |
| Descripción | Multifunction PCM CODEC (Voice Signal Processor) | |
| Fabricantes | OKI electronic componets | |
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E2U0060-18-84
¡¡SemicondSucetormiconductor
MSM7731-01
Multifunction PCM CODEC (Voice Signal Processor)
This versionM: ASMug7.713919-801
GENERAL DESCRIPTION
The MSM7731 is an LSI device developed for portable, handsfree communication with built-in
line echo canceler, acoustic echo canceler, and transmission signal noise canceler. Built-in to the
voice signal interface is a linear CODEC for the analog interface on the acoustic-side, and a linear
CODEC for the analog interface on the line-side. On the line-side, in addition to the analog
interface, there is also a m-law PCM/16-bit linear digital interface.
Equipped with gain and mute controls for data transmission and reception, a m-law PCM/16-
bit linear digital interface for memo recording and message output, and transfer clock and sync
clock generators for digital communication, this device is ideally suited for a handsfree system.
FEATURES
• Single 3 V power supply operation (2.7 V to 3.6 V)
• Built-in 2-channel (line and acoustic) echo canceler
Echo attenuation : 35 dB (typ.)
Cancelable echo delay time :
Line echo canceler + acoustic echo canceler : Tlined = 27 ms (max.),
Tacoud = 59 ms – Tlined (max.)
Acoustic echo canceler only :
Tacoud = 59 ms (max.)
• Built-in transmission signal noise canceler
Noise attenuation: 13 dB (typ.) for white noise
40 dB (typ.) for single tone
• Built-in 2-channel CODEC
Synchronous transmission and reception enables full duplex operation
• Built-in analog input gain amp stage (max. gain = 30 dB)
• Analog output configuration: Push-pull drive (can drive a 1.2 kW load)
• Built-in transmit slope filter
• Digital interface coding formats: m-law PCM, 16-bit linear (2's complement)
• Digital interface sync formats:
Normal-sync, short-frame-sync
• Built-in digital transmission clock generators
Sync clock (SYNC):
8 kHz output
Transmission clock (BCLK): 64 kHz output (m-law PCM)/128 kHz
output (16-bit linear)
• Digital transmission rate
External input:
64 kbps to 2048 kbps
Internal generation:
64 kbps (m-law PCM)/128 kbps (16-bit linear)
• Fixed digital interface sync clock (SYNC) enables automatic power-down
• Master clock frequency: 19.2 MHz
Compatible with crystal oscillator and crystal
• Low power consumption
Operating mode:
typ. 105mW (when VDD = 3.0 V)
Power-down mode:
typ. 0.3mW (when VDD = 3.0 V)
• Control by both the serial microcomputer interface and parallel port is possible
• Transmit/receive mute function, transmit/receive programmable gain setting
• Package: 64-pin plastic QFP (QFP64-P-1414-0.80-BK) (Product name: MSM7731-01GA)
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1 page  
¡ Semiconductor
MSM7731-01
PIN FUNCTIONAL DESCRIPTION
AIN, AGSX
These are the acoustic analog input and level adjusting pins. The AIN pin is connected to the
inverting input of the internal amp and the AGSX pin is connected to the amp output. For level
adjustment, refer to the diagram below (Figure 1). At power-down reset, the AGSX pin goes to
a high impedance state.
AVFRO, AOUT, APWI
These are the acoustic analog output and level adjusting pins. The AVFRO pin is an audio
output and can directly drive 20 kW. The AOUT pin is an analog output and can directly drive
a load of 1.2 kW. For level adjustment, refer to the diagram below (Figure 1). At power-down
reset, these output pins go to a high impedance state.
LIN, LGSX
These are the line analog input and level adjusting pins. The LIN pin is connected to the
inverting input of the internal amp and the LGSX pin is connected to the amp output. For level
adjustment, refer to the diagram below (Figure 1). At power-down reset, the LGSX pin goes to
a high impedance state. If LIN is not used, short the LIN and LGSX pins together.
LVFRO, LOUT, LPWI
These are the line analog output and level adjusting pins. The LVFRO pin is an audio output
and can directly drive 20 kW. The LOUT pin is an analog output and can directly drive a load
of 1.2 kW. For level adjustment, refer to the diagram below (Figure 1). At power-down reset,
these output pins go to a high impedance state. If LOUT is not used, short the LPWI and LOUT
pins together.
LINEEN
This is the power-down control pin for the line CODEC. A logic "0" continues normal operation
and a logic "1" powers down only the line CODEC. If the line CODEC is not used, power down
the line CODEC and short the LIN pin to the LGSX pin and the LPWI pin to the LOUT pin. This
procedure results in the low consumption of electrical power. At power-down, the output pins
go to a high impedance state. Since this pin is ORed with CR0-B5 of the control register, set the
pin to a logic "0" when controlling power-down by the control register. If the pin setting is
changed, reset must be activated by either the PDN/RST pin or the PDN/RST bit (CR0-B7).
VAGSX/VI=R2/R1
£30
R2≥20kW
Microphone
VI
C1 R1
0.1mF
+
–
10mF
AGSX Acoustic CODEC
Line CODEC
R2
AIN
SG
to ENCODER
–
+
VREF
AVFRO
R3 from DECODER
APWI
C2 R4
Speaker
VO
Speaker amp
VO/VAVFRO=R3/R4
R3≥20kW
AOUT
Acoustic side (microphone, speaker)
–
+
Reception signal
Transmission signal
LGSX
LIN
LVFRO
LPWI
LOUT
LINEEN
Figure 1 Analog Interface
Same as the acoustic
analog interface
Line side (portable phone)
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5 Page 
¡ Semiconductor
MSM7731-01
LGC/AGC
This pin turns ON or OFF the gain control function to control the input level and prevent
howling by means of gain controls (GainL/A) provided in the RinL/A inputs of the echo
canceler. The gain controller adjusts the RIN input level when it is –10 dBm0 or above, and it
has the control range of 0 to –8.5 dB. A logic "0" turns the function ON and a logic "1" turns the
function OFF. Since this pin is ORed with the CR4-B0 and CR5-B0 bits of the control register,
set the pin to a logic "0" when controlling by the control register. Because data is shifted into this
pin in synchronization with the rising edge of the SYNC signal, hold the data at the pin for 250
ms or longer. For further details, refer to the electrical characteristics.
Notes:
Lxx/Axx: In the above, Lxx refers to line echo canceler control pins and Axx to acoustic echo
canceler control pins.
xxL/xxA: In the above pin descriptions, xxL refers to line echo canceler functions and xxA to
acoustic echo canceler functions.
GLPADTHR
This is the mode control pin for the attenuators (LPADL/A) provided in the SinL/A inputs and
the amplifiers (GPADL/A) provided in the SoutL/A outputs of the echo canceler. A logic "0"
selects the "through mode" and a logic "1" selects the normal mode (PAD operation). The levels
are set by the CR10 register. Settings of ±18, ±12, ±6 and 0 dB are possible. The default setting
is ±12 dB. If the echo return loss (value of returned echo) is amplified, set the LPAD level such
that echo return loss will be attenuated. It is recommended to set the GPAD level to the positive
level equal to the LPAD level. Since this pin is ORed with the CR1-B2 bit of the control register,
set the pin to a logic "0" when controlling by the control register. Because data is shifted into this
pin in synchronization with the rising edge of the SYNC signal, hold the data at the pin for 250
ms or longer. For further details, refer to the electrical characteristics.
NCTHR
This is the noise canceler "through mode" control pin. In the "through mode" the noise canceler
is halted and data is directly output. A logic "0" selects the normal mode (noise canceler
operation) and a logic "1" selects the "through mode". Since this pin is ORed with the CR1-B0
bit of the control register, set the pin to a logic "0" when controlling by the control register.
Because data is shifted into this pin in synchronization with the rising edge of the SYNC signal,
hold the data at the pin for 250 ms or longer. For further details, refer to the electrical
characteristics. When this pin is changed from normal mode to "through mode", approximately
20 ms of data dropout will occur.
SLPTHR
This is the "through mode" control pin for the transmit slope filter. In the "through mode", the
filter is halted and data is directly output. A logic "0" selects the normal mode (slope filter
operation) and a logic "1" selects the "through mode". Since this pin is ORed with the CR1-B1
bit of the control register, set the pin to a logic "0" when controlling by the control register.
Because data is shifted into this pin in synchronization with the rising edge of the SYNC signal,
hold the data at the pin for 250 ms or longer. For further details, refer to the electrical
characteristics.
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