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PDF MN6155 Data sheet ( Hoja de datos )
| Número de pieza | MN6155 | |
| Descripción | PLL LSI with Built-In Prescaler | |
| Fabricantes | Panasonic Semiconductor | |
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For Communications Equipment
MN6155
PLL LSI with Built-In Prescaler
Overview
The MN6155 is a CMOS LSI for a phase-locked loop
(PLL) frequency synthesizer with serial data parameter
input.
It consists of a two-coefficient prescaler, variable
frequency divider, phase comparator, and charge pump.
It offers high-speed operation on a low power supply
voltage (1.0 to 1.4 V) and low power consumption (1.65
mW for VDD=1.1 V, FIN= RIN=90 MHz).
Other features include intermittent operation by the
power save (PS) control signal and high-speed pull-in that
rapidly corrects the phase differences occurring at the start
of operation.
It also offers two choices for the reference signal: self-
excited operation using the built-in inverter amplifier or
use of an external, separately excited oscillator.
Features
Low power supply voltage: VDD=1.0 to 1.4V
Low power consumption: 1.65mW(VDD=1.10V,
FIN=90MHz, RIN=90MHz)
High-speed operation: FIN=90MHz, RIN=90MHz
(VDD=1.1V)
Frequency dividing ratios in reference frequency
dividing stage
6 to 131,070 for RSL at "H" level
(even number setting is available)
272 to 131,071 for RSL at "L" level
Frequency dividing ratios for comparator stage: 272
to 262,143
Power supply pin for built-in charge pump
VCP=2.5 to 3.2V
Output monitor pins for both comparator and reference
frequency dividing stages
Pin Assignment
XIN
XOUT
FV
VDD
DOP
VSS
VCP
FIN
1 16
2 15
3 14
4 13
5 12
6 11
7 10
89
(TOP VIEW)
SSOP016-P-0225
RIN
RSL
LC
FR
PS
LE
DATA
CLK
1 page  
For Communications Equipment
MN6155
Note on Setting Frequency Dividing Data Input
1) Frequency dividing data input
(1) Reference side
Data input direction
MSB
LSB
Control bits
17-bit frequency dividing data
1 bit 1 bit
Frequencey Write selection
dividing stage "H" level
selection "H" level
CLK
12
17 18
19
"L"
DATA
MSB
LE
LSB
(2) Comparating side
Data input direction
*1
Control bits
CLK
3-bit test data
3 bits "L" level
1 23
18-bit frequency dividing data
1 bit
1 bit
45
Frequencey Write selection
dividing stage "H" level
selection "L" level
21 22
23
"L"
DATA
MSB
LSB
LE
Notes
1.*1: Preceding the input of the frequency dividing data for the comparating side, input test pattern consisting
of three "L" level bits to produce normal operation. Never use any other pattern.
2. When the power is first applied, internal operation remains in an unstable state until data is written. To
eliminate the risk of excessive current consumption, keep the PS pin at "L" level.
3. When the power is first applied, the data settings are indeterminate. Always write data to the chip before
starting operation.
4. Enter the data to fill the entire latch:
Reference side: 19 bits (17 bits for the frequency divider setting and 2 for control bits)
Comparating side: 23 bits (3 bits for the test pattern, 18 bits for the frequency divider setting, and 2 for
control bits)
5. Drive the LE pin at "L" level while writing the data.
6. "H" level input from the LE pin causes the chip to read the data only when the CLK pin and the DATA pin
are both at "L" level.
7. Writes are possible when the PS pin is either "H" or "L" level.
8. Input the data MSB first.
9. The data are inputted at the rising edge of the CLK signal.
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet MN6155.PDF ] | |
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