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PDF CY7C1372D Data sheet ( Hoja de datos )
| Número de pieza | CY7C1372D | |
| Descripción | 18-Mbit (512 K × 36/1 M × 18) Pipelined SRAM | |
| Fabricantes | Cypress | |
| Logotipo |  |
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CY7C1370D
CY7C1372D
18-Mbit (512 K × 36/1 M × 18) Pipelined
SRAM with NoBL™ Architecture
18-Mbit (512 K × 36/1 M × 18) Pipelined SRAM with NoBL™ Architecture
Features
■ Pin-compatible and functionally equivalent to ZBT™
■ Supports 250-MHz bus operations with zero wait states
❐ Available speed grades are 250, 200, and 167 MHz
■ Internally self-timed output buffer control to eliminate the need
to use asynchronous OE
■ Fully registered (inputs and outputs) for pipelined operation
■ Byte write capability
■ 3.3 V core power supply (VDD)
■ 3.3 V/2.5 V I/O power supply (VDDQ)
■ Fast clock-to-output times
❐ 2.6 ns (for 250 MHz device)
■ Clock enable (CEN) pin to suspend operation
■ Synchronous self-timed writes
■ Available in JEDEC-standard Pb-free 100-pin TQFP, Pb-free
and non Pb-free 65-ball FBGA package
■ IEEE 1149.1 JTAG-compatible boundary scan
■ Burst capability – linear or interleaved burst order
■ “ZZ” sleep mode option and stop clock option
Selection Guide
Maximum access time
Maximum operating current
Maximum CMOS standby current
Description
Functional Description
The CY7C1370D and CY7C1372D are 3.3 V, 512 K × 36 and
1 M × 18 synchronous pipelined burst SRAMs with No Bus
Latency™ (NoBL logic, respectively. They are designed to
support unlimited true back-to-back read/write operations with
no wait states. The CY7C1370D and CY7C1372D are equipped
with the advanced (NoBL) logic required to enable consecutive
read/write operations with data being transferred on every clock
cycle. This feature dramatically improves the throughput of data
in systems that require frequent write/read transitions. The
CY7C1370D and CY7C1372D are pin compatible and
functionally equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. The clock
input is qualified by the clock enable (CEN) signal, which when
deasserted suspends operation and extends the previous clock
cycle.
Write operations are controlled by the byte write selects
(BWa–BWd for CY7C1370D and BWa–BWb for CY7C1372D)
and a write enable (WE) input. All writes are conducted with
on-chip synchronous self-timed write circuitry.
Three synchronous chip enables (CE1, CE2, CE3) and an
asynchronous output enable (OE) provide for easy bank
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tristated during
the data portion of a write sequence.
For a complete list of related documentation, click here.
250 MHz
2.6
350
70
200 MHz
3.0
300
70
167 MHz
3.4
275
70
Unit
ns
mA
mA
Errata: For information on silicon errata, see “Errata” on page 30. Details include trigger conditions, devices affected, and proposed workaround.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-05555 Rev. *S
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 17, 2014
1 page  
CY7C1370D
CY7C1372D
Pin Configurations (continued)
Figure 2. 165-ball FBGA (13 × 15 × 1.4 mm) pinout [2, 3]
123
A NC/576M
B NC/1G
A
A
CE1
CE2
C DQPc NC VDDQ
D
DQc
DQc
VDDQ
E
DQc
DQc
VDDQ
F
DQc
DQc
VDDQ
G
DQc
DQc
VDDQ
H NC NC NC
J
DQd
DQd
VDDQ
K
DQd
DQd
VDDQ
L
DQd
DQd
VDDQ
M
DQd
DQd
VDDQ
N DQPd NC VDDQ
P NC/144M NC/72M
A
R MODE NC/36M A
CY7C1370D (512 K × 36)
4
BWc
BWd
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A
5
BWb
BWa
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
TDI
6
CE3
CLK
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
A1
7
CEN
WE
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
TDO
A TMS A0 TCK
8
ADV/LD
OE
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A
A
9
A
A
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A
A
10 11
A NC
A NC
NC DQPb
DQb DQb
DQb DQb
DQb DQb
DQb DQb
NC ZZ
DQa DQa
DQa DQa
DQa DQa
DQa DQa
NC DQPa
A NC/288M
AA
Notes
2. Errata: The ZZ ball (H11) needs to be externally connected to ground. For more information, see “Errata” on page 30.
3. Errata: The JTAG testing should be performed with these devices in BYPASS mode as the JTAG functionality is not guaranteed. For more information, see “Errata”
on page 30.
Document Number: 38-05555 Rev. *S
Page 5 of 35
5 Page 
CY7C1370D
CY7C1372D
Partial Write Cycle Description
The Partial Write Cycle Description for CY7C1370D follows. [13, 14, 15, 16]
Function (CY7C1370D)
Read
Write – No bytes written
Write Byte a – (DQa and DQPa)
Write Byte b – (DQb and DQPb)
Write Bytes b, a
Write Byte c – (DQc and DQPc)
Write Bytes c, a
Write Bytes c, b
Write Bytes c, b, a
Write Byte d – (DQd and DQPd)
Write Bytes d, a
Write Bytes d, b
Write Bytes d, b, a
Write Bytes d, c
Write Bytes d, c, a
Write Bytes d, c, b
Write All Bytes
WE
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Partial Write Cycle Description
The Partial Write Cycle Description for CY7C1372D follows. [13, 14, 15, 16]
Function (CY7C1372D)
Read
Write – No Bytes Written
Write Byte a – (DQa and DQPa)
Write Byte b – (DQb and DQPb)
Write Both Bytes
WE
H
L
L
L
L
BWd
X
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
BWc
X
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
BWb
X
H
H
L
L
BWb
X
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
BWa
X
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
BWa
X
H
L
H
L
Notes
13. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for ALL Chip Enables active. BWx = L signifies at least one Byte Write Select is active, BWx = Valid
signifies that the desired byte write selects are asserted, see Truth Table on page 10 for details.
14. Write is defined by WE and BWX. See Write Cycle Description table for details.
15. When a write cycle is detected, all I/Os are tristated, even during byte writes.
16. Table only lists a partial listing of the byte write combinations. Any Combination of BWX is valid Appropriate write will be done based on which byte write is active.
Document Number: 38-05555 Rev. *S
Page 11 of 35
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CY7C1372D.PDF ] | |
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