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PDF MC74HCT14A Data sheet ( Hoja de datos )
| Número de pieza | MC74HCT14A | |
| Descripción | Hex Schmitt-Trigger Inverter | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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MC74HCT14A
Hex Schmitt-Trigger
Inverter with LSTTL
Compatible Inputs
High−Performance Silicon−Gate CMOS
The MC74HCT14A may be used as a level converter for interfacing
TTL or NMOS outputs to high−speed CMOS inputs.
The HCT14A is useful to “square up” slow input rise and fall times.
Due to the hysteresis voltage of the Schmitt trigger, the HCT14A finds
applications in noisy environments.
Features
• Output Drive Capability: 10 LSTTL Loads
• TTL/NMOS−Compatible Input Levels
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 4.5 to 5.5 V
• Low Input Current: 1.0 mA
• In Compliance With the JEDEC Standard No. 7.0 A Requirements
• Chip Complexity: 72 FETs or 18 Equivalent Gates
• NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
• These Devices are Pb−Free, Halogen Free and are RoHS Compliant
LOGIC DIAGRAM
1
A1
2
Y1
3
A2
4
Y2
5
A3
6
Y3
9
A4
8
Y4
11
A5
10
Y5
13
A6
12
Y6
Y=A
PIN 14 = VCC
PIN 7 = GND
http://onsemi.com
SOIC−14 NB
D SUFFIX
CASE 751A
TSSOP−14
DT SUFFIX
CASE 948G
PIN ASSIGNMENT
A1
Y1
A2
Y2
A3
Y3
GND
1
2
3
4
5
6
7
14 VCC
13 A6
12 Y6
11 A5
10 Y5
9 A4
8 Y4
MARKING DIAGRAMS
14
HCT14AG
AWLYWW
1
SOIC−14 NB
14
HCT
14A
ALYWG
G
1
TSSOP−14
A
L, WL
Y, YY
W, WW
G or G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
FUNCTION TABLE
Input
A
L
H
Output
Y
H
L
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
October, 2014 − Rev. 14
1
Publication Order Number:
MC74HCT14A/D
1 page  
MC74HCT14A
PACKAGE DIMENSIONS
TSSOP−14
CASE 948G
ISSUE B
0.15 (0.006) T U S
2X L/2 14
L
PIN 1
IDENT.
1
14X K REF
0.10 (0.004) M T U S V S
N 0.25 (0.010)
8
M
B
−U− N
F
7 DETAIL E
0.15 (0.006) T U S
A
−V−
K
K1
ÇÇÇÉÉÇÇÇÉÉÇÇÇÉÉJ J1
SECTION N−N
0.10 (0.004)
−T− SEATING
PLANE
D
C
G
H DETAIL E
SOLDERING FOOTPRINT*
7.06
1
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
−W−
MILLIMETERS INCHES
DIM MIN MAX MIN MAX
A 4.90 5.10 0.193 0.200
B 4.30 4.50 0.169 0.177
C −−− 1.20 −−− 0.047
D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030
G 0.65 BSC
0.026 BSC
H 0.50 0.60 0.020 0.024
J 0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K 0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L 6.40 BSC
0.252 BSC
M 0_ 8_ 0_ 8_
0.65
PITCH
14X
0.36
14X
1.26
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
5
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| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet MC74HCT14A.PDF ] | |
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