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PDF MC74HCT245A Data sheet ( Hoja de datos )
| Número de pieza | MC74HCT245A | |
| Descripción | Octal 3-State Noninverting Bus Transceiver with LSTTL Compatible Inputs | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de MC74HCT245A (archivo pdf) en la parte inferior de esta página. Total 8 Páginas | ||
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Octal 3-State Noninverting
Bus Transceiver with
LSTTL Compatible Inputs
High–Performance Silicon–Gate CMOS
The MC54/74HCT245A is identical in pinout to the LS245. This device
may be used as a level converter for interfacing TTL or NMOS outputs to
High Speed CMOS inputs.
The MC54/74HCT245A is a 3–state noninverting transceiver that is
used for 2–way asynchronous communication between data buses. The
device has an active–low Output Enable pin, which is used to place the
I/O ports into high–impedance states. The Direction control determines
whether data flows from A to B or from B to A.
• Output Drive Capability: 15 LSTTL Loads
• TTL/NMOS Compatible Input Levels
• Outputs Directly Interface to CMOS, NMOS and TTL
• Operating Voltage Range: 4.5 to 5.5 V
• Low Input Current: 1.0 µA
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 304 FETs or 76 Equivalent Gates
A
DATA
PORT
A1 2
A2 3
A3 4
A4 5
A5 6
A6 7
A7 8
A8 9
LOGIC DIAGRAM
18 B1
17 B2
16 B3
15 B4
14 B5
13 B6
12 B7
11 B8
B
DATA
PORT
MC54/74HCT245A
20
1
J SUFFIX
CERAMIC PACKAGE
CASE 732–03
20
1
20
1
N SUFFIX
PLASTIC PACKAGE
CASE 738–03
DW SUFFIX
SOIC PACKAGE
CASE 751D–04
20
1
SD SUFFIX
SSOP PACKAGE
CASE 940C–03
20
1
DT SUFFIX
TSSOP PACKAGE
CASE 948E–02
ORDERING INFORMATION
MC54HCTXXXAJ
Ceramic
MC74HCTXXXAN Plastic
MC74HCTXXXADW SOIC
MC74HCTXXXASD SSOP
MC74HCTXXXADT TSSOP
PIN ASSIGNMENT
DIRECTION
A1
A2
A3
1
2
3
4
20 VCC
19 OUTPUT ENABLE
18 B1
17 B2
DIRECTION 1
OUTPUT ENABLE 19
PIN 20 = VCC
PIN 10 = GND
ÎÎÎÎÎÎÎÎÎÎÎÎÎDesign Criteria
Value Units
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInternal Gate Count*
76 ea
ÎÎÎÎÎÎÎÎÎÎÎÎÎInternal Gate Propagation Delay
1.0 ns
ÎÎÎÎÎÎÎÎÎÎÎÎÎInternal Gate Power Dissipation
5.0 µW
ÎÎÎÎÎÎÎÎÎÎÎÎÎSpeed Power Product
0.005
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ*Equivalent to a two–input NAND gate.
pJ
A4 5
A5 6
A6 7
A7 8
A8 9
GND 10
16 B3
15 B4
14 B5
13 B6
12 B7
11 B8
FUNCTION TABLE
Control Inputs
Output
Enable Direction
Operation
L L Data Transmitted from Bus B to Bus A
L H Data Transmitted from Bus A to Bus B
HX
X = Don’t Care
Buses Isolated (High–Impedance State)
2/97
© Motorola, Inc. 1997
3–1
REV 7
1 page  
EXPANDED LOGIC DIAGRAM
A1 2
A2 3
A3 4
A
DATA
PORT
A4 5
A5 6
A6 7
A7 8
A8 9
DIRECTION 1
OUTPUT ENABLE 19
MC54/74HCT245A
18 B1
17 B2
16 B3
15 B4
14 B5
B
DATA
PORT
13 B6
12 B7
11 B8
High–Speed CMOS Logic Data
DL129 — Rev 6
3–5
MOTOROLA
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet MC74HCT245A.PDF ] | |
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