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PDF MC74HCT373A Data sheet ( Hoja de datos )
| Número de pieza | MC74HCT373A | |
| Descripción | Octal 3-State Noninverting Transceiver Latch with LSTTL-Compatible Inputs | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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MC74HCT373A
Octal 3-State Noninverting
Transparent Latch with
LSTTL-Compatible Inputs
High–Performance Silicon–Gate CMOS
The MC74HCT373A may be used as a level converter for
interfacing TTL or NMOS outputs to High–Speed CMOS inputs.
The HCT373A is identical in pinout to the LS373.
The eight latches of the HCT373A are transparent D–type latches.
While the Latch Enable is high the Q outputs follow the Data Inputs.
When Latch Enable is taken low, data meeting the setup and hold
times becomes latched.
The Output Enable does not affect the state of the latch, but when
Output Enable is high, all outputs are forced to the high–impedance
state. Thus, data may be latched even when the outputs are not
enabled.
The HCT373A is identical in function to the HCT573A, which has
the input pins on the opposite side of the package from the output pins.
This device is similar in function to the HCT533A, which has
inverting outputs.
• Output Drive Capability: 15 LSTTL Loads
• TTL/NMOS–Compatible Input Levels
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 4.5 to 5.5 V
• Low Input Current: 1.0 µA
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 196 FETs or 49 Equivalent Gates
http://onsemi.com
20
1
20
1
PDIP–20
N SUFFIX
CASE 738
SOIC WIDE–20
DW SUFFIX
CASE 751D
MARKING
DIAGRAMS
20
MC74HCT373AN
AWLYYWW
1
20
HCT373A
AWLYYWW
1 20
20
1
TSSOP–20
DT SUFFIX
CASE 948G
HCT
373A
ALYW
1
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
PIN ASSIGNMENT
ENABLE A
A1
YB4
A2
YB3
A3
YB2
A4
YB1
GND
1
2
3
4
5
6
7
8
9
10
20 VCC
19 ENABLE B
18 YA1
17 B4
16 YA2
15 B3
14 YA3
13 B2
12 YA4
11 B1
© Semiconductor Components Industries, LLC, 2000
March, 2000 – Rev. 8
ORDERING INFORMATION
Device
Package Shipping
MC74HCT373AN
PDIP–20 1440 / Box
MC74HCT373ADW SOIC–WIDE 38 / Rail
MC74HCT373ADWR2 SOIC–WIDE 1000 / Reel
MC74HCT373ADT
TSSOP–20 75 / Rail
MC74HCT373ADTR2 TSSOP–20 2500 / Reel
1 Publication Order Number:
MC74HCT373A/D
1 page  
MC74HCT373A
EXPANDED LOGIC DIAGRAM
D0
3
D
Q
D1
4
D
Q
D2
7
D
Q
D3
8
D
Q
D4
13
D
Q
D5
14
D
Q
D6
17
D
Q
D7
18
D
Q
LATCH 11
ENABLE
OUTPUT 1
ENABLE
LE LE LE LE LE LE LE LE
2 5 6 9 12 15 16 19
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
tr
INPUT D
tPLH
Q
2.7 V
1.3 V
0.3 V
90%
1.3 V
10%
tTLH
Figure 1.
SWITCHING WAVEFORMS
tf
3V
GND
tPHL
tTHL
LATCH ENABLE
Q
tw
1.3 V
3V
1.3 V
GND
tPLH tPHL
1.3 V
Figure 2.
OUTPUT
ENABLE
Q
Q
1.3 V
tPZL tPLZ
1.3 V
tPZH tPHZ
1.3 V
Figure 3.
3V
GND
HIGH
IMPEDANCE
10% VOL
90% VOH
HIGH
IMPEDANCE
INPUT D
LATCH ENABLE
VALID
1.3 V
tsu
th
1.3 V
Figure 4.
3V
GND
3V
GND
http://onsemi.com
5
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| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet MC74HCT373A.PDF ] | |
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