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PDF MT5C1001 Data sheet ( Hoja de datos )
| Número de pieza | MT5C1001 | |
| Descripción | SRAM | |
| Fabricantes | ASI | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de MT5C1001 (archivo pdf) en la parte inferior de esta página. Total 13 Páginas | ||
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Austin Semiconductor, Inc.
SRAM
MT5C1001
Limited Availability
1M x 1 SRAM
SRAM MEMORY ARRAY
AVAILABLE AS MILITARY
SPECIFICATIONS
• SMD 5962-92316
• MIL-STD-883
FEATURES
• High Speed: 20, 25, 35, and 45
• Battery Backup: 2V data retention
• Low power standby
• Single +5V (+10%) Power Supply
• Easy memory expansion with CE\ and OE\ options.
• All inputs and outputs are TTL compatible
• Three-state output
OPTIONS
• Timing
20ns access
25ns access
35ns access
45ns access
55ns access
70ns access
MARKING
-20
-25
-35
-45
-55*
-70*
• Package(s)
Ceramic DIP (400 mil)
Ceramic LCC
Ceramic Flatpack
Ceramic SOJ
C No. 109
EC No. 207
F No. 303
DCJ No. 501
• Operating Temperature Ranges
Industrial (-40oC to +85oC)
IT
Military (-55oC to +125oC)
XT
• 2V data retention/low power L
*Electrical characteristics identical to those provided for the
45ns access devices.
For more products and information
please visit our web site at
www.austinsemiconductor.com
PIN ASSIGNMENT
(Top View)
28-Pin DIP (C)
(400 MIL)
A10 1
A11 2
A12 3
A13 4
A14 5
A15 6
NC 7
A16 8
A17 9
A18 10
A19 11
Q 12
WE\ 13
Vss 14
28 Vcc
27 A9
26 A8
25 A7
24 A6
23 A5
22 A4
21 NC
20 A3
19 A2
18 A1
17 A0
16 D
15 CE\
32-Pin LCC (EC)
32-Pin SOJ (DCJ)
A10 1
A11 2
A12 3
NC 4
A13 5
A14 6
A15 7
NC 8
A16 9
A17 10
A18 11
A19 12
NC 13
Q 14
WE\ 15
Vss 16
32 Vcc
31 NC
30 A9
29 A8
28 A7
27 A6
26 A5
25 A4
24 A3
23 NC
22 A2
21 NC
20 A1
19 A0
18 D
17 CE\
32-Pin Flat Pack (F)
A10
A11
A12
NC
A13
A14
A15
NC
A16
A17
A18
A19
NC
Q
WE\
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
3 2 Vcc
3 1 NC
3 0 A9
2 9 A8
2 8 A7
2 7 A6
2 6 A5
2 5 A4
2 4 A3
2 3 NC
2 2 A2
2 1 NC
2 0 A1
1 9 A0
18 D
1 7 CE\
GENERAL DESCRIPTION
The MT5C1001 employs low power, high-performance
silicon-gate CMOS technology. Static design eliminates the
need for external clocks or timing strobes while CMOS circuitry
reduces power consumption and provides for greater
reliability.
For flexibility in high-speed memory applications, ASI
offers chip enable (CE\) and output enable (OE\) capability.
These enhancements can place the outputs in High-Z for addi-
tional flexibility in system design. Writing to these devices is
accomplished when write enable (WE|) and CE\ inputs are both
LOW. Reading is accomplished when WE\ remains HIGH while
CE\ and OE\ go LOW. The devices offer a reduced power
standby mode when disabled. This allows system designs to
achieve low standby power requirements.
The “L” version provides an approximate 50 percent
reduction in CMOS standby current (ISBC2) over the standard
version.
All devices operation from a single +5V power supply
and all inputs and outputs are fully TTL compatible.
MT5C1001
Rev. 2.0 2/00
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1
1 page  
Austin Semiconductor, Inc.
SRAM
MT5C1001
Limited Availability
ACTEST CONDITIONS
Input pulse levels ................................... Vss to 3.0V
Input rise and fall times ....................................... 5ns
Input timing reference levels ............................. 1.5V
Output reference levels ..................................... 1.5V
Output load .............................. See Figures 1 and 2
167Ω
167Ω
Q 30pF VTH = 1.73V Q 5pF VTH = 1.73V
NOTES
1. All voltages referenced to VSS (GND).
2. -3V for pulse width < 20ns
3. ICC is dependent on output loading and cycle rates.
The specified value applies with the outputs
unloaded, and f = 1 Hz.
tRC (MIN)
4. This parameter is guaranteed but not tested.
5. Test conditions as specified with the output loading
as shown in Fig. 1 unless otherwise noted.
6. tLZCE, tLZWE, tLZOE, t HZCE, tHZOE and tHZWE are
specified with CL = 5pF as in Fig. 2. Transition is
measured ±200mV typical from steady state voltage,
Fig. 1 Output Load
Equivalent
Fig. 2 Output Load
Equivalent
allowing for actual tester RC time constant.
7. At any given temperature and voltage condition,
tHZCE is less than tLZCE, and tHZWE is less than tLZWE and
tHZOE is less than tLZOE.
8. WE\ is HIGH for READ cycle.
9. Device is continuously selected. Chip enables and
output enables are held in their active state.
10. Address valid prior to, or coincident with, latest
occurring chip enable.
11. tRC = Read Cycle Time.
12. Chip enable (CE\) and write enable (WE\) can initiate and
terminate a WRITE cycle.
DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only)
DESCRIPTION
VCC for Retention Data
Data Retention Current
Chip Deselect to Data
Retention Time
Operation Recovery Time
CONDITIONS
CE\ > (VCC - 0.2V)
and
VIN > (VCC - 0.2V)
or < 0.2V
VCC = 2V
VCC = 3V
SYMBOL
VDR
ICCDR
tCDR
tR
MIN
2
0
tRC
MAX
--
1.0
1.5
--
UNITS
V
mA
NOTES
mA
ns 4
ns 4, 11
MT5C1001
Rev. 2.0 2/00
LOW Vcc DATA RETENTION WAVEFORM
VCC
tCDR
CE\
VIH
VIL
111122223333444455556666777788889999
DATA RETENTION MODE
4.5V
VDR > 2V
4.5V
VDR
tR
111122223333444455556666111177772111122288883222233343343344
111122223333DON’T CARE
1111222233334444UNDEFINED
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5
5 Page 
Austin Semiconductor, Inc.
SRAM
MT5C1001
Limited Availability
MECHANICAL DEFINITIONS*
ASI Case #501 (Package Designator DCJ)
SMD #5962-92316, Case Outline U
A
e D1
b
D
B1
E
A2
E2
E1
SYMBOL
A
A2
B1
b
D
D1
E
E1
E2
e
SMD SPECIFICATIONS
MIN MAX
0.135
0.153
0.026
0.036
0.030
0.040
0.015
0.019
0.812
0.828
0.745
0.760
0.405
0.415
0.435
0.445
0.360
0.380
0.050 BSC
NOTE: These dimensions are per the SMD. ASI's package dimensional limits
may differ, but they will be within the SMD limits.
*All measurements are in inches.
MT5C1001
Rev. 2.0 2/00
11
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet MT5C1001.PDF ] | |
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