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PDF MT5C2564 Data sheet ( Hoja de datos )
| Número de pieza | MT5C2564 | |
| Descripción | SRAM | |
| Fabricantes | ASI | |
| Logotipo |  |
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Austin Semiconductor, Inc.
SRAM
MT5C2564
64K x 4 SRAM
SRAM MEMORY ARRAY
AVAILABLE AS MILITARY
SPECIFICATIONS
• SMD 5962-88681
• MIL-STD-883
FEATURES
• High Speed: 15, 20, 25, 35, 45, 55, and 70
• Battery Backup: 2V data retention
• Low power standby
• High-performance, low-power, CMOS double-metal
process
• Single +5V (+10%) Power Supply
• Easy memory expansion with CE\
• All inputs and outputs are TTL compatible
OPTIONS
• Timing
15ns access
20ns access
25ns access
35ns access
45ns access
55ns access
70ns access
MARKING
-15
-20
-25
-35
-45
-55*
-70*
• Package(s)
Ceramic DIP (300 mil)
Ceramic LCC
C No. 106
EC No. 204
• Operating Temperature Ranges
Industrial (-40oC to +85oC)
IT
Military (-55oC to +125oC)
XT
• 2V data retention/low power L
*Electrical characteristics identical to those provided for the 45ns
access devices.
PIN ASSIGNMENT
(Top View)
24-Pin DIP (C)
(300 MIL)
A0 1
A1 2
A2 3
A3 4
A4 5
A5 6
A6 7
A7 8
A8 9
A9 10
CE\ 11
Vss 12
24 Vcc
23 A15
22 A14
21 A13
20 A12
19 A11
18 A10
17 DQ4
16 DQ3
15 DQ2
14 DQ1
13 WE\
28-Pin LCC (EC)
A2 4
A3 5
A4 6
A5 7
A6 8
A7 9
A8 10
A9 11
CE\ 1 2
3 2 1 28 27
26 A15
25 A14
24 A13
23 A12
22 A11
21 A10
2 0 DQ4
1 9 DQ3
1 8 DQ2
13 14 15 16 17
GENERAL DESCRIPTION
The Austin Semiconductor SRAM family employs
high-speed, low-power CMOS and are fabricated using double-
layer metal, double-layer polysilicon technology.
For flexibility in high-speed memory applications,
Austin Semiconductor offers chip enable (CE\) on all organiza-
tions. This enhancement can place the outputs in High-Z for
additional flexibility in system design. The x4 configuration
features common data input and output.
Writing to these devices is accomplished when write
enable (WE\) and CE\ inputs are both LOW. Reading is accom-
plished when WE\ remains HIGH and CE\ goes LOW. The
device offers a reduced power standby mode when disabled.
This allows system designs to achieve low standby power re-
quirements.
These devices operate from a single +5V power sup-
ply and all inputs and outputs are fully TTL compatible.
For more products and information
please visit our web site at
www.austinsemiconductor.com
MT5C2564
Rev. 2.0 11/00
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1
1 page  
Austin Semiconductor, Inc.
SRAM
MT5C2564
ACTEST CONDITIONS
Input pulse levels ...................................... Vss to 3.0V
Input rise and fall times ......................................... 5ns
Input timing reference levels ................................ 1.5V
Output reference levels ....................................... 1.5V
Output load ................................. See Figures 1 and 2
NOTES
1. All voltages referenced to VSS (GND).
2. -3V for pulse width < 20ns
3. ICC is dependent on output loading and cycle rates.
The specified value applies with the outputs
unloaded, and f = 1 Hz.
tRC (MIN)
4. This parameter is guaranteed but not tested.
5. Test conditions as specified with the output loading
as shown in Fig. 1 unless otherwise noted.
6. tLZCE, tLZWE, tLZOE, tHZCE, tHZOE and tHZWE are
specified with CL = 5pF as in Fig. 2. Transition is
measured ±200mV typical from steady state voltage,
167Ω
167Ω
Q 30pF VTH = 1.73V Q 5pF VTH = 1.73V
Fig. 1 Output Load
Equivalent
Fig. 2 Output Load
Equivalent
allowing for actual tester RC time constant.
7. At any given temperature and voltage condition,
tHZCE is less than tLZCE, and tHZWE is less than tLZWE and
tHZOE is less than tLZOE.
8. WE\ is HIGH for READ cycle.
9. Device is continuously selected. Chip enable is held in
its active state.
10. Address valid prior to, or coincident with, latest
occurring chip enable.
11. tRC = Read Cycle Time.
12. Chip enable (CE\) and write enable (WE\) can initiate and
terminate a WRITE cycle.
DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only)
DESCRIPTION
CONDITIONS
SYM MIN MAX UNITS
VCC for Retention Data
VDR
2
---
V
Data Retention Current
CE\ > (VCC - 0.2V)
VIN > (VCC - 0.2V)
or < 0.2V
VCC = 2V ICCDR
VCC = 3V
1 mA
2 mA
Chip Deselect to Data
Retention Time
tCDR
0
---
ns
Operation Recovery Time
tR tRC
ns
NOTES
4
4, 11
LOW Vcc DATA RETENTION WAVEFORM
MT5C2564
Rev. 2.0 11/00
VCC
tCDR
CE\
VIH
VIL
11112222333344445555666677778888
DATA RETENTION MODE
4.5V
VDR > 2V
4.5V
VDR
tR
11112222333344445555111166662222777733331111888844222244
111122223333DON’T CARE
1111222233334444UNDEFINED
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5
5 Page 
Austin Semiconductor, Inc.
SRAM
MT5C2564
ASI TO DSCC PART NUMBER
CROSS REFERENCE*
ASI Package Designator C
ASI Part #
MT5C2564C-20/883C
MT5C2564C-25/883C
MT5C2564C-35/883C
MT5C2564C-45/883C
MT5C2564C-55/883C
MT5C2564C-70/883C
SMD Part #
5962-8868106LA
5962-8868105LA
5962-8868101LA
5962-8868102LA
5962-8868103LA
5962-8868104LA
ASI Package Designator EC
ASI Part #
MT5C2564EC-20/883C
MT5C2564EC-25/883C
MT5C2564EC-35/883C
MT5C2564EC-45/883C
MT5C2564EC-55/883C
MT5C2564EC-70/883C
SMD Part #
5962-8868106XA
5962-8868105XA
5962-8868101XA
5962-8868102XA
5962-8868103XA
5962-8868104XA
* ASI part number is for reference only. Orders received referencing the SMD part number will be processed per the SMD.
MT5C2564
Rev. 2.0 11/00
11
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet MT5C2564.PDF ] | |
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