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PDF EM614163A Data sheet ( Hoja de datos )
| Número de pieza | EM614163A | |
| Descripción | 256K x 16 High Speed EDO DRAM | |
| Fabricantes | ETRONTECH | |
| Logotipo |  |
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EtronTech
Em614163A-30/35/40/45
256K x 16 High Speed EDO DRAM
Preliminary
Features
• Fast Access Time: 30/35/40/45ns
• Fast EDO Page Cycle Time: 13.3/15/16/18ns
• EDO Page Mode Operation
• Single +5V ¡Ó10% Power Supply
• Low Power Dissipation
• Individual Byte Control via Dual CAS Inputs
• Three Refresh Modes
• 512-Cycle Refresh in 8ms(9 rows and 9 columns)
• TTL Compatible
• 40-Pin, 400-mil Plastic SOJ Package, or
40/44-Pin, 400-mil Plastic TSOP-II Package.
Ordering Information
Part Number
Speed
Em614163A-30
EM614163TS-30
Em614163A-35
EM614163TS-35
Em614163A-40
30ns
30ns
35ns
35ns
40ns
EM614163TS-40
Em614163A-45
EM614163TS-45
40ns
45ns
45ns
Key Specifications
Package
SOJ
TSOP-II
SOJ
TSOP-II
SOJ
TSOP-II
SOJ
TSOP-II
Speed tRAC
-30 30ns
-35 35ns
-40 40ns
-45 45ns
tCAC
9ns
10ns
11ns
12ns
tAA
16ns
18ns
20ns
22ns
tOEA
9ns
9ns
10ns
10ns
tRC
53ns
60ns
66ns
75ns
tPC
13.3ns
15ns
16ns
18ns
Overview
The Em614163A-30/35/40/45 is a high speed
EDO(Extended Data Output) DRAM organized in
262,144 words by 16 bits. It supports EDO Page
Mode and 16-bit data width for high data bandwidth
applications. The EDO Page Mode is an
accelerated access that provides a shorter page
cycle and a faster data access time than the
traditional Fast Page Mode.
Compared with Fast Page Mode DRAM, the
EDO DRAM data output will be held valid after CAS
goes HIGH, as long as RAS and OE are held LOW
and WE is held HIGH. This feature allows CAS
Pin Assignment (Top View)
40-Pin SOJ
Vcc
I/ O0
I/ O1
I/ O2
I/ O3
Vcc
I/ O4
I/ O5
I/ O6
I/ O7
NC
NC
WE
RAS
NC
A0
A1
A2
A3
Vcc
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
Pin Names
40/44-Pin TSOP-II
Vss
I/ O1 5
I/ O1 4
I/ O1 3
I/ O1 2
Vss
I/ O1 1
I/ O1 0
I/ O9
I/ O8
NC
LCAS
UCAS
OE
A8
A7
A6
A5
A4
Vss
Vcc
I/ O0
I/ O1
I/ O2
I/ O3
Vcc
I/ O4
I/ O5
I/ O6
I/ O7
NC
NC
WE
RAS
NC
A0
A1
A2
A3
Vcc
1
2
3
4
5
6
7
8
9
10
13
14
15
16
17
18
19
20
21
22
44 Vss
43 I/O15
42 I/O14
41 I/O13
40 I/O12
39 Vss
38 I/O11
37 I/O10
36 I/O9
35 I/O8
32 NC
31 LC AS
30 UCAS
29 OE
28 A8
27 A7
26 A6
25 A5
24 A4
23 Vss
A0 - A8
RAS
UCAS
LCAS
WE
OE
I/O0 - I/O15
VCC
VSS
NC
Address Inputs
Row Address Strobe
Column Address Strobe
(Upper Byte Control)
Column Address Strobe
(Lower Byte Control)
Write Enable
Output Enable
Data Input/Output
+5V Power Supply
Ground
No Connection
precharge time to occur without the output data
going invalid. Therefore, the EDO CAS timing can be
condensed to carry more data out in a given period.
The Em614163A-30/35/40/45 fully utilizes the
EDO Page Mode advantages. It allows 512 random
access within a page with a fast cycle time as short
as 13.3/15/16/18 ns.
The Em614163A-30/35/40/45 is ideally suitable
for high performance graphics frame buffers, CD-
ROMs, disk drivers, set top boxes, and DSP
applications.
Etron Technology, Inc.
1F, No. 1, Prosperity Rd. 1, Science-Based Industrial Park, Hsinchu, Taiwan, R.O.C.
TEL: (886)-3-5782345 FAX: (886)-3-5779001
Etro n Techn olo gy, Inc. reserves th e right to make chan ges to its pro ducts and specificat ion s
without notice.
April 1997
1 page  
EtronTech
Em614163A-30/35/40/45
Recommended Operating Conditions
Parameter
Symbol Min Typ
Max
Supply voltage
VSS 0 0
0
Input high voltage
VCC 4.5 5.0 5.5
VIH 2.4 ¡Ð VCC + 0.3
Input low voltage
VIL - 0.5 ¡Ð 0.8
Notes:
1. All voltage referenced to VSS.
2. The supply voltage with all VCC pins must be the same level.
The supply voltage with all VSS pins must be the same level.
3. VIL(min.) = - 1.2V for pulse width ¡Ø30ns.
Unit
V
V
V
V
Notes
2
1, 2
1
1, 3
DC Characteristics
TA = 0 to +70°C; Vcc = +5V ± 10%, Vss = 0V
Em614163A
Parameter
Symbol
Test Conditions
-30/35/40/45
Unit Notes
Min Max
RAS cycling
Operating current ICC1 LCAS , UCAS cycling
¡Ð 280/250/225/200 mA 1, 2
tRC = min.
RAS , LCAS , UCAS = VIH
Standby current
ICC2 Dout = High-Z
¡Ð 2 mA
RAS , LCAS , UCAS , OE =
VCC - 0.2V
¡Ð 1 mA
Dout = High-Z
RAS -only refresh
current
ICC3 RAS cycling, CAS = VIH ¡Ð 280/250/225/200 mA
tRC = min.
2
Standby current
CAS -before-RAS
refresh current
ICC5
RAS = VIH
LCAS , UCAS = VIL
Dout = enable
ICC6 tRC = min.
RAS , CAS cycling
¡Ð 5 mA 1
¡Ð 280/250/225/200 mA
Fast page mode
current
ICC7 tPC = min.
¡Ð 280/250/225/200 mA 1, 3
Input leakage
ILI 0V¡ÕVin¡ÕVCC
-10
10 µA
current
Output leakage
current
ILO 0V¡ÕVout¡ÕVCC
Dout = Disable
-10
10 µA
Output high voltage VOH IOH = - 2.5 mA
2.4
V
Output low voltage VOL IOL = + 2.1 mA
0.4 V
Notes:
1. ICC depends on output load condition when the device is selected. ICC-max is specified at the output open
condition.
2. Address can be changed once or less while RAS = VIL.
3. Address can be changed once or less while LCAS and UCAS = VIL.
4. All the VCC pins shall be supplied with the same voltage. And all the VSS pins shall be supplied with the
same voltage.
Preliminary
5
April 1997
5 Page 
EtronTech
Em614163A-30/35/40/45
• Early Write Cycle
RAS
UCAS
LCAS
tT
tRC
tRAS
t RP
tRCD
tCSH
tRSH
tCAS
t CRP
Address
WE
DIN
t ASR
t RAH
Row
tASC
tCAH
Column
t WCS
tWCH
t DS t DH
Din
DOUT
OPEN
Preliminary
11
April 1997
11 Page | ||
| Páginas | Total 23 Páginas | |
| PDF Descargar | [ Datasheet EM614163A.PDF ] | |
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