|
|
PDF MC145201 Data sheet ( Hoja de datos )
| Número de pieza | MC145201 | |
| Descripción | 2.0 GHz PLL Frequency Synthesizers | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de MC145201 (archivo pdf) en la parte inferior de esta página. Total 23 Páginas | ||
|
No Preview Available !
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MC145200/D
2.0 GHz PLL Frequency
Synthesizers
Include On–Board 64/65 Prescalers
The MC145200 and MC145201 are single–package synthesizers with serial
interfaces capable of direct usage up to 2.0 GHz. A special architecture makes
these PLLs very easy to program because a byte–oriented format is utilized.
Due to the patented BitGrabber™ registers, no address/steering bits are
required for random access of the three registers. Thus, tuning can be
accomplished via a 3–byte serial transfer to the 24–bit A register. The interface
is both SPI and MICROWIRE™ compatible.
Each device features a single–ended current source/sink phase detector
output and a double–ended phase detector output. Both phase detectors have
linear transfer functions (no dead zones). The maximum current of the
single–ended phase detector output is determined by an external resistor tied
from the Rx pin to ground. This current can be varied via the serial port.
The MC145200 features logic–level converters and high–voltage phase/
frequency detectors; the detector supply may range up to 9.5 V. The MC145201
has lower–voltage phase/frequency detectors optimized for single–supply
systems of 5 V ±10%.
Each part includes a differential RF input which may be operated in a
single–ended mode. Also featured are on–board support of an external crystal
and a programmable reference output. The R, A, and N counters are fully
programmable. The C register (configuration register) allows the parts to be
configured to meet various applications. A patented feature allows the C
register to shut off unused outputs, thereby minimizing system noise and
interference.
In order to have consistent lock times and prevent erroneous data from being
loaded into the counters, on–board circuitry synchronizes the update of the A
register if the A or N counters are loading. Similarly, an update of the R register
is synchronized if the R counter is loading.
The double–buffered R register allows new divide ratios to be presented to
the three counters (R, A, and N) simultaneously.
• Maximum Operating Frequency: 2000 MHz @ Vin = 200 mV p–p
• Operating Supply Current: 12 mA Nominal
• Operating Supply Voltage Range (VDD and VCC Pins): 4.5 to 5.5 V
• Operating Supply Voltage Range of Phase Detectors (VPD Pin) —
MC145200: 8.0 to 9.5 V
MC145201: 4.5 to 5.5 V
• Current Source/Sink Phase Detector Output Capability: 2 mA Maximum
• Gain of Current Source/Sink Phase/Frequency Detector Controllable via
Serial Port
• Operating Temperature Range: – 40 to + 85°C
• R Counter Division Range: (1 and) 5 to 8191
• Dual–Modulus Capability Provides Total Division up to 262,143
• High–Speed Serial Interface: 4 Mbps
• OUTPUT A Pin, When Configured as Data Out, Permits Cascading of Devices
• Two General–Purpose Digital Outputs — OUTPUT A: Totem–Pole (Push–Pull)
OUTPUT B: Open–Drain
• Power–Saving Standby Feature with Orderly Recovery for Minimizing Lock
Times, Standby Current: 30 µA
• Evaluation Kit Available (Part Numbers MC145200EVK and MC145201EVK)
• See Application Note AN1253/D for Low–Pass Filter Design, and
AN1277/D for Offset Reference PLLs for Fine Resolution or Fast Hopping
MC145200
MC145201
20
1
F SUFFIX
SOG PACKAGE
CASE 751J
DT SUFFIX
TSSOP
20
CASE 948D
1
ORDERING INFORMATION
MC145200F
MC145201F
MC145200DT
MC145201DT
SOG Package
SOG Package
TSSOP
TSSOP
PIN ASSIGNMENT
REFout
LD
φR
φV
VPD
PDout
GND
Rx
TEST 1
fin
1
2
3
4
5
6
7
8
9
10
20 REFin
19 Din
18 CLK
17 ENB
16 OUTPUT A
15 OUTPUT B
14 VDD
13 TEST 2
12 VCC
11 fin
BitGrabber is a trademark of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp.
REV 4
1/98 TN98012300
©MOMoTtoOroRla,OInLc.A1998
MC145200•MC145201
1
1 page  
SWITCHING WAVEFORMS
tf tr
90%
CLK 50%
10%
OUTPUT A
(DATA OUT)
90%
50%
10%
tw
1/fclk
tPLH
tTLH
tw
tPHL
tTHL
Figure 1.
VDD ENB 50%
GND
tPLH tPHL
OUTPUT A
50%
tPLZ tPZL
OUTPUT B
10%
Figure 2.
VDD
GND
50%
VALID
Din 50%
tsu th
CLK 50%
Figure 3.
tw
VDD ENB 50%
GND
tsu th
VDD
GND CLK 50%
FIRST
CLK
LAST
CLK
tw
trec
VDD
GND
VDD
GND
Figure 4.
TEST POINT
DEVICE
UNDER
TEST
CL*
*Includes all probe and fixture capacitance.
Figure 5. Test Circuit
DEVICE
UNDER
TEST
+V
TEST POINT
7.5 kΩ
CL*
*Includes all probe and fixture capacitance.
Figure 6. Test Circuit
MOTOROLA
MC145200•MC145201
5
5 Page 
VPD
Positive Power Supply (Pin 5)
This pin supplies power to both phase/frequency detectors
A and B. The voltage applied on this pin must be no less than
the potential applied to the VDD pin. The maximum voltage
can be + 9.5 V with respect to the GND pin for the MC145200
and + 5.5 V for the MC145201.
For optimum performance, VPD should be bypassed to
GND using a low–inductance capacitor mounted very close
to these pins. Lead lengths on the capacitor should be
minimized.
GND
Ground (Pin 7)
Common ground.
100 ns MINIMUM
ENB
CLK
1234
Din
5
1234
5
1234
5
NOTE: It may not be convenient to control the ENB or CLK pins during power up per the Pin Descriptions. If this is the case, the part may
be initialized through the serial port as shown in the figure above. The sequence is similar to accessing the registers except that the
CLK must remain high at least 100 ns after ENB is brought high. Note that 3 groups of 5 bits are needed.
Figure 13. Initializing the PLL through the Serial Port
MC145200
t tNominal PDout Spurious Current vs fR Frequency
(1 V PDout VPD – 1V)
fR
(kHz)
Current
(RMS nA)
10 1.6
20 5.3
50 22
100 95
200 320
MC145201
t tNominal PDout Spurious Current vs fR Frequency
(1 V PDout VPD – 1V)
fR
(kHz)
Current
(RMS nA)
10 3.6
20 4.6
50 17
100 75
200 244
NOTE: For information on spurious current measurement see AN1253/D, “An Improved PLL Design Method Without ωn and ζ”.
Table 2. PDout Current, C1 = Low with OUTPUT A NOT
Selected as “Port”; Also, Default Mode When
OUTPUT A Selected as “Port”
C3 C2 PDout Current
0 0 70%
0 1 80%
1 0 90%
1 1 100%
Table 3. PDout Current, C1 = High with OUTPUT A NOT
Selected as “Port”
C3 C2 PDout Current
0 0 25%
0 1 50%
1 0 75%
1 1 100%
MOTOROLA
MC145200•MC145201
11
11 Page | ||
| Páginas | Total 23 Páginas | |
| PDF Descargar | [ Datasheet MC145201.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| MC145200 | 2.0 GHz PLL Frequency Synthesizers | Motorola Semiconductors |
| MC145201 | 2.0 GHz PLL Frequency Synthesizers | Motorola Semiconductors |
| MC145202 | Low-Voltage 2.0 GHz PLL Frequency Synthesizer | Motorola Semiconductors |
| MC14520B | (MC14518B / MC14520B) DUAL UP COUNTERS | Motorola Semiconductors |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |