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PDF SK7072x Data sheet ( Hoja de datos )
| Número de pieza | SK7072x | |
| Descripción | Multi-Rate DSL Data Pump Chipt Set | |
| Fabricantes | Intel | |
| Logotipo |  |
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SK70720 and SK70721
Multi-Rate DSL Data Pump Chip Set
Datasheet
The Multi-Rate DSL Data Pump is a complete, variable-rate transceiver that provides full duplex
communication on two wires using echo-canceller-with-hybrid and 2B1Q line coding
technology. It provides symmetrical line rates from 272 to 784 kbps. Performance specifications
are defined at the 272, 400, 528, and 784 kbps data rates which provide a payload of 4, 6, 8, or
12 64 kbps channels with a 16 kbps overhead channel. The MDSL Data Pump also supports
applications where the payload is unchannellized.
The MDSL Data Pump chip set consists of two devices:
s SK70720 MDSL Digital Signal Processor (MDSP)
s SK70721 Integrated Analog Front-End (IAFE)
The IAFE is a fully integrated CMOS analog front-end IC which includes transmitter line
drivers, filters, and 2B1Q encoding functions along with the receiver hybrid, AGC, A-to-D
converter modulator and VCXO functions. The MDSP incorporates all digital signal processing
required for A/D conversion, echo-cancellation, data scrambling and adaptive equalization as
well as transceiver activation state machine control.
Applications
s High speed residential Internet access
s Wireless base station to switch access
s Extended Range fractional T1/E1 transport s WAN access for LAN routers
s 4 to 12-channel digital pair-gain
s Video Conferencing
As of January 15, 2001, this document replaces the Level One document
SK70720 and SK70721 — Multi-Rate DSL Data Pump Chip Set.
Order Number: 249209-001
January 2001
1 page  
Multi-Rate DSL Data Pump Chip Set — SK70720 and SK70721
15 IAFE DC Electrical Characteristics (Over Recommended Range)......................40
16 IAFE Transmitter Electrical Parameters (Over Recommended Range)..............41
17 IAFE Receiver Electrical Parameters (Over Recommended Range) ..................42
18 MDSP Absolute Maximum Ratings .....................................................................45
19 MDSP Recommended Operating Conditions......................................................45
20 MDSP DC Electrical Characteristics (Over Recommended Range) ...................46
21 MDSL Data Interface Timing Specifications (Figure 22) .....................................46
22 MDSP/Microprocessor Interface Timing Specifications (Figure 19 & Figure 20) 49
23 General System and Hardware Mode Timing .....................................................49
24 Register Summary...............................................................................................52
25 Main Control Register WR0.................................................................................52
26 Interrupt Mask Register WR2 ..............................................................................53
27 Read Coefficient Select Register WR3 ...............................................................54
28 Main Status Register RD0...................................................................................54
29 Receiver Gain Word Register..............................................................................55
30 Noise Margin Register RD2
(Noise Margin Coding)55
31 Coefficient Read Register ...................................................................................57
32 Activation Status Register RD5 ...........................................................................57
33 Receiver AGC and FFE Step Gain Register RD6 ...............................................58
Datasheet
5
5 Page 
Multi-Rate DSL Data Pump Chip Set — SK70720 and SK70721
Figure 3. SK70720 MDSP Pin Assignments
6 5 4 3 2 1 44 43 42 41 40
RFP
RDATA
ADDR3(ACTVNG)
RDATA_ST
TDATA
TFP
MSTR_CK
SLAVE_CK
CK_EN
MODE
BIT_CK
7 39
8 38
9 37
10 36
11 35
12 Part # SK70720PE XX Rev # 34
13
LOT # XXXXXX
FPO # XXXXXXXX
33
14 32
15 31
16 30
17 29
18 19 20 21 22 23 24 25 26 27 28
D3(RPTR)
D2(ILMT)
D1(DEACTVTD)
D0(LOS)
READ
WRITE
CHIPSEL
INT(TMR_EXP)
TEST
ACTIVE
n/c
NOTE: Pin Functions in Hardware Control Mode are shown in parentheses.
Package Topside Markings
Marking
Part #
Rev #
Lot #
FPO #
Definition
Unique identifier for this product family.
Identifies the particular silicon “stepping” — refer to the specification update for additional stepping
information.
Identifies the batch.
Identifies the Finish Process Order.
Datasheet
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SK7072x.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
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| SK7072x | Multi-Rate DSL Data Pump Chipt Set | Intel |
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