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PDF STK14D88-3 Data sheet ( Hoja de datos )
| Número de pieza | STK14D88-3 | |
| Descripción | 32K x 8 SRAM / CMOS | |
| Fabricantes | Simtek | |
| Logotipo |  |
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STK14D88-3
32K x 8 AutoStoreTM nvSRAM
QuantumTrapTM CMOS
Nonvolatile Static RAM
FEATURES
• 25ns, 35ns and 45ns Access Times
• “Hands-off” Automatic STORE on Power Down
with only a small capacitor
• STORE to QuantumTrap™ Nonvolatile
Elements is Initiated by Software , device pin
or AutoStore™ on Power Down
• RECALL to SRAM Initiated by Software or
Power Restore
• Unlimited READ, WRITE and RECALL Cycles
• 5mA Typical ICC at 200ns Cycle Time
• 1,000,000 STORE Cycles to QuantumTrap™
• 100-Year Data Retention to QuantumTrap™
• Single 3V +20%, -10% Operation
• Commercial and Industrial Temperatures
• SSOP and SOIC Packages
• RoHS Compliance
DESCRIPTION
The Simtek STK14D88-3 is a fast static RAM with a
nonvolatile element in each memory cell. The
embedded nonvolatile elements incorporate
Simtek’s QuantumTrap™ technology producing the
world’s most reliable nonvolatile memory. The
SRAM provides unlimited read and write cycles,
while independent, nonvolatile data resides in the
highly reliable QuantumTrapTM cell. Data transfers
from the SRAM to the nonvolatile elements (the
STORE operation) takes place automatically at
power down. On power up, data is restored to the
SRAM (the RECALL operation) from the nonvolatile
memory. Both the STORE and RECALL operations
are also available under software control.
BLOCK DIAGRAM
A5
A6
A7
A8
A9
A11
A12
A13
A14
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
Quatum Trap
512 X 512
STATIC RAM
ARRAY
512 X 512
STORE
RECALL
COLUMN I/O
COLUMN DEC
A0 A1 A2 A3 A4 A10
VCC
VCAP
POWER
CONTROL
STORE/
RECALL
CONTROL
HSB
SOFTWARE
DETECT
A13 – A0
G
Figure 1. Block Diagram
E
W
January 2005
1 Document Control #ML0033 rev 1.1
1 page  
STK14D88-3
SRAM READ CYCLES #1 & #2
SYMBOLS
NO.
#1 #2
Alt.
PARAMETER
1
tELQV
tACS
2
tAVAVc
tAVAVc
tRC
3 tAVQVd
tAA
4
tGLQV
tOE
5 tAXQXd
tOH
6
tELQX
tLZ
7
tEHQZe
tHZ
8
tGLQX
tOLZ
9
tGHQZe
tOHZ
10
tELICCb
tPA
11
tEHICCb
tPS
Chip Enable Access Time
Read Cycle Time
Address Access Time
Output Enable to Data Valid
Output Hold after Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
Notes
c: W must be high during SRAM READ cycles
d: Device is continuously selected with E and G both low
e: Measured ± 200mV from steady state output voltage
f: HSB must remain high during READ and WRITE cycles.
STK14D88-3-25
MIN MAX
25
25
25
12
3
3
10
0
10
0
25
SRAM READ CYCLE #1: Address Controlledc,d,f
2
tAVAV
ADDRESS
DQ (DATA OUT)
5
tAXQX
3
tAVQV
DATA VALID
STK14D88-3-35
MIN MAX
35
35
35
15
3
3
13
0
13
0
35
STK14D88-3-45
MIN MAX
45
45
45
20
3
3
15
0
15
0
45
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SRAM READ CYCLE #2: E Controlledc,f
ADDRESS
E
6
tELQX
2
tAVAV
1
tELQV
G
DQ (DATA OUT)
ICC
8
tGLQX
10
tELICCH
STANDBY
4
tGLQV
ACTIVE
11
tEHICCL
7
tEHQZ
9
tGHQZ
DATA VALID
January 2005
5 Document Control #ML0033 rev 1.1
5 Page 
DEVICE OPERATION
STK14D88-3
nvSRAM
The STK14D88-3 nvSRAM is made up of two
functional components paired in the same physical
cell. These are a SRAM memory cell and a
nonvolatile QuantumTrap™ cell. The SRAM memory
cell operates as a standard fast static RAM. Data in
the SRAM can be transferred to the nonvolatile cell
(the STORE operation), or from the nonvolatile cell
to SRAM (the RECALL operation). This unique
architecture allows all cells to be stored and recalled
in parallel. During the STORE and RECALL
operations SRAM READ and WRITE operations are
inhibited. The STK14D88-3 supports unlimited reads
and writes just like a typical SRAM. In addition, it
provides unlimited RECALL operations from the
nonvolatile cells and up to 1 million STORE
operations.
SRAM READ
The STK14D88-3 performs a READ cycle whenever
E and G are low while W and HSB are high.
The address specified on pins A14-0 determines which
of the 32,752 data bytes will be accessed. When the
READ is initiated by an address transition, the
outputs will be valid after a delay of tAVQV (READ
cycle #1). If the READ is initiated by E or G , the
outputs will be valid at tELQV or at tGLQV, whichever is
later (READ cycle #2). The data outputs will
repeatedly respond to address changes within the
tAVQV access time without the need for transitions on
any control input pins, and will remain valid until
another address change or until E or G is brought
high, or W or HSB is brought low.
VCAP
VCC
VCC
W
Figure 4: AutoStoreTM Mode
SRAM WRITE
A WRITE cycle is performed whenever E and W
are low and HSB is high. The address inputs must be
stable prior to entering the WRITE cycle and must
remain stable until either E or W goes high at the
end of the cycle. The data on the common I/O pins
DQ0-7 will be written into the memory if it is valid tDVWH
before the end of a W controlled WRITE or tDVEH
before the end of an E controlled WRITE.
It is recommended that G be kept high during the
entire WRITE cycle to avoid data bus contention on
common I/O lines. If G is left low, internal circuitry will
turn off the output buffers tWLQZ after W goes low.
AutoStore™ OPERATION
The STK14D88-3 stores data to nvSRAM using one of
three storage operations. These three operations are
Hardware Store, activated by HSB , Software Store,
actived by an address sequence, and AutoStore™, on
device power down.
AutoStore™ operation is a unique feature of Simtek
QuantumTrap™ technology and is enabled by default
on the STK14D88-3.
During normal operation, the device will draw current
from Vcc to charge a capacitor connected to the Vcap
pin. This stored charge will be used by the chip to
perform a single STORE operation. If the voltage on
the Vcc pin drops below Vswitch, the part will
automatically disconnect the Vcap pin from Vcc. A
STORE operation will be initiated with power provided
by the Vcap capacitor.
Figure 4 shows the proper connection of the storage
capacitor (Vcap) for automatic store operation. Refer
to the DC CHARACTERISTICS table for the size of
Vcap. The voltage on the Vcap pin is driven to 5V by a
charge pump internal to the chip. A pull up should be
placed on W to hold it inactive during power up.
To reduce unneeded nonvolatile stores, AutoStore™
and Hardware Store operations will be ignored unless
at least one WRITE operation has taken place since
the most recent STORE or RECALL cycle. Software
initiated STORE cycles are performed regardless of
whether a WRITE operation has taken place. The
HSB signal can be monitored by the system to detect
an AutoStore™ cycle is in progress.
January 2005
11 Document Control #ML0033 rev 1.1
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet STK14D88-3.PDF ] | |
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