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PDF ST75C520 Data sheet ( Hoja de datos )
| Número de pieza | ST75C520 | |
| Descripción | HIGH SPEED FAX MODEM DATA PUMP | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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ST75C520
HIGH SPEED FAX MODEM DATA PUMP
. ITU-T V.17, V.29, V.27ter, V.21 WITH FAX
SUPPORT
. ITU-T V.23, V.21, BELL 103
. V.17, V.29 (T104), V.27ter SHORT TRAINS
. V.33 HALF-DUPLEX
. 1800Hz OR 1700Hz CARRIER
. SINGLE CHIP COMPLETE DATA PUMP
. SINGLE 5V POWER SUPPLY :
- TYPICAL ACTIVE POWER CONSUMPTION :
375mW
. - LOW POWER MODE (typ. 5mW)
EXTENDED MODES OF OPERATIONS :
- FULL IMPLEMENTATION OF THE V.17,
V.33, V.29 AND V.27ter HANDSHAKES
- AUTODIAL AND AUTOANSWER CAPABIL-
ITY
- PROGRAMMABLE TONE DETECTION AND
FSK V.21 FLAG PATTERN DETECTION
DURING HIGH SPEED RECEPTION
- PROGRAMMABLE CALL PROGRESS AND
CALL WAITING TONE DETECTORS IN-
CLUDING DTMF
- PROGRAMMABLE CLASS™ DETECTION
CAPABILITY
- WIDE DYNAMIC RANGE (>48dB)
. - A-LAW VOICE PCM MODE
VERSATILE INTERFACES :
- PARALLEL 64 x 8-BIT DUAL PORT RAM
- SYNCHRONOUS/HDLC PARALLEL DATA
HANDLING
- HDLC FRAMING SUPPORT
- V.24 INTERFACE
- FULL OPERATING STATUS REAL TIME
MONITORING
- FULL DIAGNOSTIC CAPABILITY
- DUAL 8-BIT DAC FOR CONSTELLATION
DISPLAY
PRELIMINARY DATA
DESCRIPTION
The SGS-THOMSON Microelectronics ST75C520
chip is a highly integrated modem engine, which
can operate with all currently used FAX group III
standards up to 14400bps. Full V.21, V.23 and Bell
103 full duplex modem standards are imple-
mented.
PQFP64
(Plastic Quad Flat Pack)
ORDER CODE : ST75C520 PQFP
June 1995
This is advance information on a new product now in development or undergoing evaluation. Details are subject to change without no tice.
1/45
1 page  
ST75C520
I.7 - Power Supply
Symbol
VDD
GND
AVDD
AGNDT
AGNDR
Parameter
Digital +5V (Pin 9, 25, 41). To be connected to AVDD (see below).
Digital Ground (Pin 8, 24, 40). To be connected to AGNDT and AGNDR (see below).
Analog +5V (Pin 62). To be connected to VDD (see below).
Analog Transmit Ground (Pin 64). To be connected to GND (see below).
Analog Receive Ground (Pin 59). To be connected to GND (see below).
AGNDT and AGNDR must be connected together as close as possible to the chip.
GND and AGNDR board plans should be separated, then connected together as close as possible to the
chip, at a single point. Similarly VDD and AVDD must ne connected as close as possible to the chip, at a
single point.
II - BLOCK DIAGRAMS
II.1 - Functional Block Diagram
ST75C520
SD [0..7]
(26 to 33)
DUAL RAM
INTERFACE
15 16 14
HDLC
TX
MUX
V.17, V.29, V.27
FAX TRANSMITTER
TX
ANALOG
DPLL
HDLC
RX
V.17, V.29, V.27
FAX RECEIVER
RX
ANALOG
SINTR 38
HANDSHAKE AND
STATUS REPORT
V.24
INTERFACE
RING
DETECTOR
TONE
DETECTOR
V.21 FLAG
DETECTOR
13 12 11
10
1 TXA2
2 TXA1
60 RXA1
61 RXA2
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5 Page 
ST75C520
IV.2.10 - Reset
After a hardware reset, or an INIT command, the
ST75C520 clears all its internal memories, clears
the whole dual RAM and starts to initialize the delta
sigma analog converters. As soon as these initiali-
zations are completed, the ST75C520 clears the
dual RAM address 0 (COMSYS), generates an
interrupt IT6 (command acknoledge) and is pro-
grammed to send and receive tones, the bit clock
and the sample clock are programmed to 9600Hz.
The total duration of the reset sequence is about
5ms. After that time the ST75C520 is ready to
execute commands sent by the host micro-control-
ler. The durationof the reset signal shouldbe greater
than 700ns.
IV.3 - Modem Interface
IV.3.1 - Analog Interface
The modem designer must provide a proper hybrid
interface to the ST75C520. An example of hybrid
design is given in paragraphs XII and XIII. The
inputs and outputs of the MAFE are differential,
achieving thus a better noise immunity. The D/A
converter output amplifier includes a single pole
low-pass filter, its cut-off frequency is :
Fc - 3dB # 19200Hz.
Continuous-time filtering of the analog differential
output is necessary using an off-chip amplifier and
a few external passive components.
IV.3.2 - Host Interface
The host interface is seen by the micro as a 64x8
RAM, with additional registers accessible through
an 8-bit address space. A selection Pin (INT/MOT)
allows to configure the host bus for either INTEL or
MOTOROLA type control signals.
V.1.1 - Mapping
V.1.1.1 - Command Area
The command area is located from $00 to $04.
Address $00 holds the command byte COMSYS,
and the next four locations hold the parameters
COMPAR[0..3]. The command parameters must
be entered before the command word is issued.
Once the command has been entered, the com-
mand byte is reset and an acknowledge report is
issued. A new command should not be issued
before the acknowledgecounter COMACK isincre-
mented.
V.1.1.2 - Report Area
The report area is located from address $05 to
address $07. Location $05 holds the acknowledge
counter COMACK. Each time a command is ac-
knowledged, the report bytes COMREP[0..1] (if
any) are written by the ST75C520 into locations
$06 and $07, and the content of COMACK is
incremented. This counter allows the ST75C520 to
accurately monitor the command processing.
V.1.1.3 - Status Area
The statusarea is located from address $08 to $0A.
The error status word SYSERR is located at ad-
dress $08. This error status word is updated each
time an error condition occurs. An optionalinterrup-
tion IT0 may additionally be triggered in the case
of an error condition. Locations $09 and $0A hold
the general status bytes STATUS[0..1]. The mean-
ing of the bits depends on the mode of operation,
and is described in Chapter VII. The third byte at
address $0B holds the Quality Monitor byte
STAQUA.
V - USER INTERFACE
V.1 - Dual Port Ram Description
The dual port RAM is the standard interface between
the controller and the ST75C520, for either com-
mands or data. This memory is addressedthrough a
7-bit address bus. The locations from $00 to $3F are
RAM locations, while locations from $40 to $50 are
control registers dedicated to the interrupt handling.
Several functional areas are defined in the dual port
RAM, namely :
- the command area,
- the report area,
- the status area,
- the data buffer area.
V.1.1.4 - Optional Status Area
The user can program (through the DOSR com-
mand) the three locations STAOPT[0..2] of the
Optional Status Area ($0C to $0E) for the real time
monitoring of three arbitrary memory locations.
V.1.1.5 - Data Buffer Area
The data area is made of four 8-byte buffers. Two
are dedicated to transmission and the two others
to reception. Each of the four buffers is attached to
a status byte. the meaning of the status byte de-
pends on the selected format of transmission.
Within each buffer, D0 represents the first bit in
time.
11/45
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