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PDF MAX3832UCB Data sheet ( Hoja de datos )
| Número de pieza | MAX3832UCB | |
| Descripción | +3.3V / 2.5Gbps / SDH/SONET / 4-Channel Interconnect Mux/Demux ICs with Clock Generator | |
| Fabricantes | Maxim Integrated | |
| Logotipo |  |
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19-1534; Rev 1; 10/99
+3.3V, 2.5Gbps, SDH/SONET, 4-Channel
Interconnect Mux/Demux ICs with Clock Generator
General Description
The MAX3831/MAX3832 are 4:1 multiplexers (muxes)
and 1:4 demultiplexers (demuxes) with automatic chan-
nel assignment. Operating from a single +3.3V supply,
the mux receives four parallel, 622Mbps SDH/SONET
channels. These channels are bit interleaved to gener-
ate a serial data stream of 2.488Gbps for interfacing to
an optical or an electrical driver. A 10-bit-wide elastic
buffer tolerates up to ±7.5ns skew between any parallel
data input and the reference clock. An external
155MHz reference clock is required for the on-chip PLL
to synthesize a high-frequency 2.488GHz clock for tim-
ing the outgoing data streams.
The MAX3831/MAX3832’s demux receives 2.488Gbps
serial data and the 2.488GHz clock from an external
clock/data recovery device (MAX3876), converting it to
four 622Mbps LVDS outputs. The MAX3831 provides a
622MHz LVDS clock output, and the MAX3832 pro-
vides a 155MHz LVDS clock output. An internal frame
detector looks for a 622Mbps SDH/SONET framing pat-
tern and rolls the demux to maintain proper channel
assignment at the outputs.
These devices also include an embedded pattern gen-
erator that enables a full-speed, built-in self-test (BIST).
Two different loopback modes provide system test flexi-
bility. A TTL loss-of-frame monitor is included. The
MAX3831/MAX3832 are available in 64-pin TQFP-EP
(exposed paddle) packages and are specified over the
upper commercial (0°C to +85°C) temperature range.
Pin Configuration appears at end of data sheet.
Features
o +3.3V Single Supply
o 1.45W Power Dissipation (MAX3831)
o 4-Channel Mux/Demux with Fully Integrated
2.488GHz Clock Generator
o Frame Detection Maintains Channel Assignment
o ±7.5ns Elastic Store Range
o 2.5ps RMS Serial-Data Output Random Jitter
o 8ps Serial-Data Output Deterministic Jitter
o 622Mbps LVDS Parallel Input/Output
o 2.488Gbps Serial CML Input/Output
o On-Chip Pattern Generator Provides
High-Speed BIST
o System Test Flexibility: System Loopback,
Line Loopback
o Loss-of-Frame Indicator
SDH/SONET Backplanes
High-Speed Parallel Links
Intrarack/Subrack
Interconnects
Applications
ATM Switching Networks
Line Extenders
Dense Digital Cross-
Connects
PART
MAX3831UCB
MAX3832UCB
Ordering Information
TEMP. RANGE
0°C to +85°C
0°C to +85°C
PIN-PACKAGE
64 TQFP-EP
64 TQFP-EP
Typical Application Circuit
155MHz REF
CLOCK INPUT
LVDS
4
4 LVDS
CMOS
OVERHEAD
4
LVDS 4
LVDS
TTL
0.33µF
TTL TTL
+3.3V
TTL
RSETES FIL+ FIL- TEST LOF
RCLKI+
RCLKI-
PDI1+ TO PDI4+
PDI1- TO PDI4-
PDO1+ TO PDO4+
MAX3831
MAX3832
PDO1- TO PDO4-
PCLKO+
PCLKO-
TRIEN GND
PLBEN VCC
SCLKI-
SCLKI+
SDI-
SDI+
SDO+
SDO-
LBEN
RSETFR
0.1µF
CML
MAX3876
2.5Gbps
CML CDR
TTL
TTL
2.5Gbps
OPTICAL
TRANSCEIVER
TTL
________________________________________________________________ Maxim Integrated Products 1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 1-800-835-8769.
1 page  
+3.3V, 2.5Gbps, SDH/SONET, 4-Channel
Interconnect Mux/Demux ICs with Clock Generator
(VCC = +3.3V, TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics
SERIAL-DATA OUTPUT EYE DIAGRAM
223-1 PRBS PATTERN
SERIAL-DATA OUTPUT JITTER
SUPPLY CURRENT vs. TEMPERATURE
600
500 MAX3832
400 MAX3831
300
WIDEBAND RMS
JITTER = 2.48ps
200
100
50ps/div
10
8
6
4
2
0
-2
-4
-6
-8
-10
0
ELASTIC STORE RANGE
ERROR-FREE OPERATION
CHANNEL ALIGNED TO RCLKI
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
DATA TO RCLKI DELAY AT RESET (ns)
5ps/div
100
0
-50 -25
0
25 50 75 100
TEMPERATURE (°C)
SERIAL-DATA HOLD TIME
80
60
40
20
0
-20
-50 -25
0
25 50 75 100
TEMPERATURE (°C)
SERIAL-DATA SETUP TIME
100
MAX3831
PARALLEL CLOCK-TO-DATA OUTPUT
PROPAGATION DELAY vs. TEMPERATURE
300
80 250
200
60
150
40
100
20 50
0
-50 -25 0 25 50 75 100
TEMPERATURE (°C)
0
-50 -25
0
25 50 75 100
TEMPERATURE (°C)
_______________________________________________________________________________________ 5
5 Page 
+3.3V, 2.5Gbps, SDH/SONET, 4-Channel
Interconnect Mux/Demux ICs with Clock Generator
VCC
PECL
LEVELS
RT*
RT*
0.1µF 25Ω
SDI+
50Ω 50Ω
0.1µF
100Ω
25Ω SDI-
MAX3831
MAX3832
*SELECT RT SUCH THAT THE CORRECT PECL COMMON-MODE LEVEL
IS ACHIEVED (TYPICAL PECL OUTPUT CURRENT = 14mA).
Figure 8. PECL-to-CML Interface
Layout Techniques
For best performance, use good high-frequency layout
techniques. Filter voltage supplies, keep ground con-
nections short, and use multiple vias where possible.
Use controlled-impedance transmission lines to inter-
face with the MAX3831/MAX3832 high-speed inputs
and outputs.
Place power-supply decoupling as close to VCC as
possible. To reduce feedthrough, take care to isolate
the input signals from the output signals.
VCC = 3.3V
VCC = 3.3V
PECL
OUTPUT
82Ω
SDI+
82Ω
82Ω
SDI-
82Ω
50Ω 50Ω
MAX3831
MAX3832
Figure 9. Direct Coupling of a PECL Output into the MAX3831/
MAX3832
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet MAX3832UCB.PDF ] | |
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