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PDF MAX3111E Data sheet ( Hoja de datos )
| Número de pieza | MAX3111E | |
| Descripción | RS-232 Transceivers | |
| Fabricantes | Maxim Integrated | |
| Logotipo |  |
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MAX3110E/MAX3111E
SPI/MICROWIRE-Compatible UART
and ±15kV ESD-Protected RS-232
Transceivers with Internal Capacitors
General Description
The MAX3110E/MAX3111E combine a full-featured uni-
versal asynchronous receiver/transmitter (UART) with
±15kV ESD-protected RS-232 transceivers and inte-
grated charge-pump capacitors into a single 28-pin
package for use in space-, cost-, and power-con-
strained applications. The MAX3110E/MAX3111E also
feature an SPI/QSPI™/MICROWIRE®-compatible serial
interface to save additional board space and microcon-
troller (µC) I/O pins.
A proprietary low-dropout output stage enables the
2-driver/2-receiver interface to deliver true RS-232 per-
formance down to VCC = +3V (+4.5V for MAX3110E)
while consuming only 600µA. The receivers remain
active in a hardware/software-invoked shutdown, allow-
ing external devices to be monitored while consuming
only 10µA. Each device is guaranteed to operate at up
to 230kbps while maintaining true EIA/TIA-232 output
voltage levels.
The MAX3110E/MAX3111E’s UART includes a crystal
oscillator and baud-rate generator with software-pro-
grammable divider ratios for all common baud rates
from 300baud to 230kbaud. The UART features an 8-
word-deep receive FIFO that minimizes processor over-
head and provides a flexible interrupt with four
maskable sources. Two control lines (one input and
one output) are included for hardware handshaking.
The UART and RS-232 functions can be used together
or independently since the two functions share only
supply and ground connections (the MAX3110E/
MAX3111E are hardware- and software-compatible
with the MAX3100 and MAX3222E).
Applications
Point-of-Sale (POS) Devices
Handy-Terminals
Telecom/Networking Diagnostic Ports
Industrial Front-Panel Interfaces
Hand-Held/Battery-Powered Equipment
Pin Configuration appears at end of data sheet.
†Covered by U.S. Patent numbers 4,636,930; 4,679,134;
4,777,577; 4,797,899; 4,809,152; 4,897,774; 4,999,761; and
other patents pending.
QSPI is a trademark of Motorola, Inc.
MICROWIRE is a registered trademark of National
Semiconductor Corp.
Benefits and Features
• Integration Reduces Cost and Board Space
• Integrated RS-232 Transceiver and UART in a
Single 28-Pin Package
Guaranteed 230kbps Data Rate
SPI/QSPI/MICROWIRE-Compatible µC Interface
• Internal Charge-Pump Capacitors—No External
Components Required
• Low-Power Operation Reduces Thermal Dissipation
• True RS-232 Operation Down to VCC = +3V
(MAX3111E)
• Single-Supply Operation
+5V (MAX3110E)
+3.3V (MAX3111E)
• 600µA Supply Current
• 10µA Shutdown Supply Current with Receiver
Interrupt Active
• Hardware/Software-Compatible with MAX3100 and
MAX3222E
Ordering Information
PART
MAX3110ECWI
MAX3110ECNI
TEMP.
RANGE
0°C to +70°C
0°C to +70°C
PIN-
PACKAGE
28 Wide SO
28 Plastic DIP
VCC
(V)
5
5
Ordering Information continued at end of data sheet.
Typical Application Circuit
MAX3110E
MAX3111E
SPI RS-232
CS
SCLK U
μP DIN
A
DOUT
R
T
IRQ
DB-9
1 234 5
6 789
19-1494; Rev 2; 2/15
1 page  
MAX3110E/MAX3111E
SPI/MICROWIRE-Compatible UART
and ±15kV ESD-Protected RS-232
Transceivers with Internal Capacitors
Electrical Characteristics—MAX3111E
(VCC = +3.0V to +3.6V, VA = TMIN to TMAX, unless otherwise noted. Typical values are measured for baud rate set to 9600baud at
VCC = +3.3V, TA = +25°C.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
DC CHARACTERISTICS (VCC = 3.3V, TA = +25°C)
Supply Current
ICC SHDN = VCC, no load
Supply Current with Hardware
Shutdown
ICCSHDN(H) SHDN = GND (Note 3)
Supply Current with Hardware
and Software Shutdown
ICCSHDN(H+ S) SHDN = GND SHDNi bit = 1 (Note 4)
UART OSCILLATOR INPUT (X1)
Input High Voltage
Input Low Voltage
VIH1
VIL1
Input Current
IIN1
Input Capacitance
CIN1
UART LOGIC INPUTS (DIN, SCLK, CS, RX)
Input High Voltage
VIH2
Input Low Voltage
Input Hysteresis
Input Leakage Current
VIL2
VHYST2
ILKG1
Input Capacitance
CIN2
RS-232 LOGIC INPUTS (T_IN, SHDN)
Input High Voltage
VIH3
Input Low Voltage
VIL3
Transmitter Input Hysteresis
VHYST3
Input Leakage Current
RS-232 RECEIVER INPUTS (R_IN)
IIN3
Input Voltage Range
Input High Voltage
Input Low Voltage
Input Hysteresis
Input Resistance
VIH4
VIL4
VHYST4
RIN
RS-232 ESD PROTECTION (R_IN, T_OUT)
ESD Protection
VX1 = 0 or 3.6V
SHDNi bit = 0
SHDNi bit = 1
VCC = 3.3V
TA = +25°C, VCC = 3.3V
TA = +25°C, VCC = 3.3V
TA = +25°C
Human Body Model
IEC 1000-4-2 Air Discharge
IEC 1000-4-2 Contact Discharge
MIN TYP MAX UNITS
0.45 1.4 mA
0.18 0.4 mA
1 20
0.7VCC
0.2VCC
25
2
5
µA
V
V
V
µA
pF
0.7VCC
V
0.3VCC V
165 mV
±1 µA
5 pF
2.0
0.8
500
±0.01 ±1
V
V
mV
µA
-25 +25 V
2.4 V
0.6 V
500 mV
3 5 7 kΩ
±15
±15 kV
±8
www.maximintegrated.com
Maxim Integrated | 5
5 Page 
MAX3110E/MAX3111E
SPI/MICROWIRE-Compatible UART
and ±15kV ESD-Protected RS-232
Transceivers with Internal Capacitors
SPI Interface
The MAX3110E/MAX3111E are compatible with SPI,
QSPI (CPOL = 0, CPHA = 0), and MICROWIRE serial-
interface standards (Figure 2). The MAX3110E/
MAX3111E have a unique full-duplex-only architecture
that expects a 16-bit word for DIN and simultaneously
produces a 16-bit word for DOUT regardless of which
read/write register is used. The DIN stream is moni-
tored for its first two bits to tell the UART the type of
data transfer being executed (see the Write
Configuration Register, Read Configuration Register,
Write Data Register, and Read Data Register sections).
DIN (MOSI) is latched on SCLK’s rising edge. DOUT
(MISO) should be read into the µP on SCLK’s rising
edge. The first bit (bit 15) of DOUT transitions on CS’s
falling edge, and bits 14–0 transition on SCLK’s falling
edge. Figure 3 shows the detailed serial timing specifi-
cations for the synchronous SPI port.
Only 16-bit words are expected. If CS goes high in the
middle of a transmission (any time before the 16th bit),
the sequence is aborted (i.e., data does not get written
to individual registers). Most operations, such as the
clearing of internal registers, are executed only on
CS’s rising edge. Every time CS goes low, a new 16-bit
stream is expected. An example of using the Write
Configuration Register is shown in Figure 4.
Table 1 describes the bits located in the Write Config-
uration, Read Configuration, Write Data, and Read
Data Registers. This table also describes whether the
bit is a read or a write bit and the power-on reset state
(POR) of the bits. Figure 5 shows an example of parity
and word-length control.
DIN
DOUT
MSB 14 13 12 11 10 9 8 7 6 5 4 3 2 1 LSB
MSB 14 13 12 11 10 9 8 7 6 5 4 3 2 1 LSB
CS
SCLK
(CPOL = 0, CPHA = 0)
SCLK
(CPOL = 0, CPHA = 1)
SCLK
(CPOL = 1, CPHA = 0)
SCLK
(CPOL = 1, CPHA = 1)
Figure 2. Compatible CPOL and CPHA Timing Modes
COMPATIBLE
WITH MAX3110E/MAX3111E
NOT COMPATIBLE
WITH MAX3110E/MAX3111E
CS
SCLK
DIN
DOUT
tCSS
tCSO
tDS
tDH
tDV
•••
tCH
tCL
•••
•••
•••
Figure 3. Detailed Serial Timing Specifications for the Synchronous SPI Port
www.maximintegrated.com
tDO
tCSH tCS1
tTR
Maxim Integrated | 11
11 Page | ||
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| PDF Descargar | [ Datasheet MAX3111E.PDF ] | |
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