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PDF SP8858MGHCAR Data sheet ( Hoja de datos )

Número de pieza SP8858MGHCAR
Descripción 15GHz Professional Synthesiser
Fabricantes Mitel Networks 
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SP8858
1·5GHz Professional Synthesiser
Supersedes March 1997 version, DS3843 - 3.0
DS3843 - 4.1 July 1998
The SP8858 is a single chip synthesiser intended for PLL
signal synthesis applications up to 1.5GHz and includes a
dual modulus prescaler (4N/N11), programmable A, M and
R dividers, digital phase detector, charge pump and lock
detect circuits.
The SP8858 is a development of the SP8853 synthesiser
with low residual phase noise, increased dynamic range
above 1GHz and an improved high gain phase detector
design that eliminates the dead-band.
The low prescaler modulus, programmable to either 16/17
or 8/9, together with the 15-bit M counter and 13-bit reference
counter make this device ideal for a diverse range of high
performance applications.
The nominal phase detector gain is set by a reference
current into pin 24 and the gain can be varied over a 4:1 range
when the device is programmed. The dividers, the phase
detector sense, the prescaler modulus and the data buffer
control logic are also programmable using the three wire
serial interface. An alternative 22-bit control word for the A
and M dividers and phase detector gain can be stored so
allowing fast frequency hopping and bandwidth switching by
simply toggling the logic level on pin 13 (F1/F2). In addition,
the A counter of the ‘active’ buffer can be programmed with
only 6 bits, allowing fast hopping to adjacent channels.
A simple exclusive - or lock detect circuit is also provided,
the sensitivity of which is determined by an external capacitor.
FEATURES
s Low Residual Phase Noise (see Reference 1)
s Operation to 1·5GHz over Full Temperature Range
s High Input Sensitivity
s Improved Linear Digital Phase Detector
s Programmable Charge Pump Current: 10µA to 2 mA
s On-chip 416/17 or 48/9 Dual Modulus Prescaler
s Three-wire Serial Data Interface
s 13-bit Reference Counter
s 15-bit M Counter
s Stores an Alternative Programming Word
s Facility to Program A counter Only
s Power Saving Standby Mode
ABSOLUTE MAXIMUM RATINGS
Supply voltage
Storage temperature
Operating temperature
Prescaler input voltage
20·3V to 17V
265°C to 1150°C
255°C to 1125°C
2·5V p-p
FREF*
POWER DOWN
VEE4
VCC4
VCC1
RF INPUT
RF INPUT
4 3 2 1 28 27 26
5 25
6 24
7 23
8 SP8858
22
9 21
10 20
11 19
12 13 14 15 16 17 18
CP OUTPUT
RPD
VCC3
GROUND
XTAL 1
XTAL2
VEE2
HC28
FREF*
POWER DOWN
VEE4
VCC4
VCC1
RF INPUT
RF INPUT
4 3 2 1 28 27 26
5 25
6 24
7 23
8
SP8858
22
9 21
10 20
11 19
12 13 14 15 16 17 18
CP OUTPUT
RPD
VCC3
GROUND
XTAL 1
XTAL2
VEE2
HP28
Fig. 1 Pin connections (top view)
ORDERING INFORMATION
SP8858 IG HCAR 240°C to 185°C (Industrial grade)
SP8858 MG HCAR 255°C to 1125°C (Military grade)
SP8858 IG HPAS 240°C to 185°C (Industrial grade)

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SP8858MGHCAR pdf
DATA
CLOCK
2V
tS
tS1tCH
FIRST DATA BIT
tCH tCL
LAST DATA BIT
tREP
2V
ENABLE
2V
tS-EN
tREP = tCH 1 tCL MIN
tS = 50ns MIN
tCH = 100ns MIN
tCL = 100ns MIN
tE = 50ns MIN
tS-EN = [(31M)N1A]4RF INPUT (Hz)150ns
OR 14REFERENCE (Hz)150ns
WHICHEVER IS APPROPRIATE
(SEE DATA ENTRY AND CONTROL)
tE
Fig. 4 DATA, CLOCK and ENABLE timing requirements
RF INPUT
MODULUS CONTROL
PRESCALER
4N / N11
A
COUNTER
RESET
M
COUNTER
RF INPUT 4(MN1A)
Fig. 5
SP8858
5

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SP8858MGHCAR arduino
The selection of C1 and R1 is often approached by using
the standard representation for the second order characteristic
equation: s212zvn1vn2 and selecting the natural-loop
frequency and the damping factor z to give the desired
response. The time constants are calculated using:
2zvn = t1K/C1 and vn2 = K/C1 so that
C1 = K/vn2 and R1 = 2zvn/K
Alternatively, the loop filter and formula shown in Fig. 10b
can be used to introduce a pole in F(s) at 21/t2 which will
provide additional roll-off in the closed loop transfer
characteristic in order to attenuate the reference sidebands.
The closed loop transfer function becomes:
fo(s)
=
[s(t11t2)11]KVCOKPD
fi(s) [C1t2s31C1s21K(t11t2)s1K]
Care must be taken when choosing C2 to ensure that the
additional pole does not unduly affect the stability margins of
the loop. In practice, a simple and useful rule of thumb is to set
the desired second order response as above and then set C2
to be 1/10 of C1. It is advisable when designing third order or
SP8858
higher order loops to use CAD tools to assess stability.
Popular analysis tools taken from control theory, such as root
locus and Bode diagrams, are useful to aid the design of the
closed loop PLL system. AN194 describes these tools in more
detail and introduces a loop filter design methodolgy aimed at
optimising the phase noise performance.
Loop filter design example
Use the demonstration board to generate a 1GHz signal
with a resolution of 500kHz (N = 5000) and reference oscillator
frequency of 40MHz. Set natural loop frequency, vn, to
2p3104 rad/s and damping factor to 0·7. The MQE001-1016
VCO gain, KVCO, is nominally 25MHz/V. Set the phase detector
output current to 2mA so that KPD = 231023/2p A/rad.
Using the above formula, calculate the loop filter R and Cs.
K = 2p32531063231023/2p35000 = 10
C1 = 10/(2p3104)32 2·531029
R1 = 230·732p3104/10 8796
C2 = C1/10 0·2531029
Realise the loop filter with C1 = 2·2nF, C2 = 220pF and
R1 = 8·2k. The single sideband phase noise specturm for
this example is shown in Fig. 11.
C1 R1
Ii(s)
+
Vo (s)
Vo (s) / Ii(s) = [s(t111]/sC1
where t1 = C1R1
Fig. 10a
C2
C1
R1
Ii(s)
+
Vo (s)
Vo (s) / Ii(s) = [s(t11t2)11]/sC1(st211)
where t1 = C1R1 and t2 = C2R1
Fig. 10b
Fig. 10 Loop filters
0
210
220
230
240
250
260
270
280
290
2100
2110
2120
2130
2140
2150
2160
2170
10Hz
100Hz
1kHz
FREQUENCY
Fig. 11
10kHz
100kHz
11

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