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PDF SP8852EIGHCAR Data sheet ( Hoja de datos )
| Número de pieza | SP8852EIGHCAR | |
| Descripción | 27GHz Parallel Load Professional Synthesiser | |
| Fabricantes | Mitel Networks | |
| Logotipo |  |
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Supersedes January 1996 version, DS4237 - 1.2
SP8852E
2·7GHz Parallel Load Professional Synthesiser
Preliminary Information
DS4237 - 2.0 June 1998
The SP8852E is one of a family of parallel load synthesisers
containing all the elements apart from the loop amplifier to
fabricate a PLL synthesis loop. Other parts in the series are
the SP8854E which has hard wired reference counter pro-
gramming and requires only a single 16-bit programming
word, and the SP8855E which is fully programmable using
hard wired links or switches.
The SP8852E is programmed using a 16-bit parallel data
bus. Data can be stored in one of two internal buffers, selected
by a single address bit on the input interface. In order to fully
program the device, two 16-bit words are required, one to
select the RF division ratio (A and M counters) and phase
detector gain, and one to set the 10-bit reference divider
count, phase detector state and sense. Once the reference
divide ratio has been set, frequency changes can be made by
a single 16-bit data load entry to the RF divider chain.
B4
B3
B2
B1
B0
0V (PRESCALER)
RF INPUT
RF INPUT
VCC (PRESCALER)
VEE
LOCK DETECT
1 44
SP8852E
STROBE
ADDRESS
NC
NC
NC
NC
NC
NC
NC
NC
NC
FEATURES
s 2·7 GHz Operating Frequency
s Single 5V Supply
s Low Power Consumption <1·3W
s High Comparison Frequency : 20MHz
s High Gain Phase Detector : 1mA/rad
s Zero ‘Dead Band’ Phase Detector
s Wide Range of RF and Reference Division Ratios
s Programming by Dual Word Data Transfer
ABSOLUTE MAXIMUM RATINGS
Supply voltage
Operating temperature
Storage temperature
Prescaler and reference input voltage
Data inputs
Junction temperature
20·3V to 16V
255°C to1100°C
265°C to 1150°C
2·5Vp-p
VCC 10·3V
VEE 20·3V
1175°C
ORDERING INFORMATION
SP8852E KG HCAR Non-standard temperature range,
255°C to 1100°C, standard product screening
SP8852E IG HCAR Industrial temperature range,
240°C to 185°C, standard product screening
HC44
*FPD and FREF outputs are reversed by the phase
detector sense bit in the F1/F2 programming word, bit
12. The above diagram is correct when bit 12 is high.
Fig. 1 Pin connections - top view
THERMAL DATA
uJC = 5°C/W
uJA = 53°C/W
ESD PROTECTION
1000V, human body model
1 page  
120
110
17
0
25
210
220
230
100MHz
TYPICAL OVERLOAD
GUARANTEED
OPERATING WINDOW
TYPICAL SENSITIVITY
1GHz
FREQUENCY
2GHz 2·7GHz
Fig. 3 Input sensitivity
10GHz
j 0.5
j 0.2
0 0.2
1·1GHz
0.5
2j 0.2
j1
j2
ZO = 50Ω
j5
12 5
50MHz
2·5GHz
2j 5
2j 0.5
2j 1
2j 2
Fig. 4 RF input impedance
SP8852E
5
5 Page 
C2
C1
FROM
CHARGE PUMP
FROM
CHARGE PUMP
REFERENCE
R2
−
+
TO VCO
Fig. 8 Third order loop filter circuit diagram
Loop Filter Design
Generally, the third order filter configuration shown in Fig. 8
gives better results than the more commonly used second order
because the reference sidebands are reduced. Three equations
are required to determine values for the three constants, where
The equations are:
t1 = C1R1
tt23
=
=
R2 (C11C2)
C2R2
t1 =
KfK0
vn2N
11vn2
t22
1
2
11vn2 t32
…(1)
t2 =
1
vn2t32
…(2)
t3
=
2tan
F0 1cos1F0
vn
…(3)
where
Kf is the phase detector gain factor in mA/radian
K0 is the VCO gain factor in radians/seconds/V
N is the division ratio from VCO to reference frequency
vn is the natural loop frequency
F0 is the phase margin, normally set to 45°
Since the phase detector used is linear over a range of 2p
radians, the phase detector gain is given by:
Phase comparator current setting
Kf =
2p
mA/radian
These values can now be substituted in equation (1) to obtain
a value for C1 and in equations (2) and (3) to determine values
for C2 and R2.
Example
Calculate values for a loop with the following parameters:
Frequency to be synthesised
Reference frequency
Division ratio
K0 VCO gain factor
F0 phase margin
Phase comparator current
1000MHz
10MHz
1000MHz/100MHz = 100
2p310MHz/V
45°
6·3mA
The phase detector gain factor Kf = 6·3/2p = 1mA/radian
SP8852E
From equation (3):
t3
=
2tan 45°1cos145°
100kHz32p
= 0·4142
628319
∴t3 = 65931029
From equation (2):
t2 =
1
(100kHz32p)2365931029
∴t2 = 3·84431026
Using these values in equation (1):
t1 =
13102332p310MHz/V
1
3[A]2
1003(100kHz32p)2
where
A
=
11vn2
11vn2
t22
t32
=11(100kHz32p)23(3·84431026)2
11(100kHz32p)23(65931029)2
1
t1 =
62832
39·48310212
6·833 2
1·1714
= 1·593102932·415
∴t1 = 3·8431029
Now, t1 = C1 ∴ C1 = 3·84nF
t2 = R2 (C11C2)
t2 = C2R2
Substituting for C2:
t2
=
R2
C11Rt32
or, R2=
t22t3
C1
=
3·84431026265931029
0·015331026
∴R2 = 829·4Ω
t3
=
C2R2
= t3
R2
= 65931029
829·4
∴C2 = 0·794nF
11
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