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PDF SP706R Data sheet ( Hoja de datos )
| Número de pieza | SP706R | |
| Descripción | +3.0V/+3.3V Low Power Microprocessor Supervisory Circuits | |
| Fabricantes | Sipex | |
| Logotipo |  |
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® SP706P/R/S/T, SP708R/S/T
+3.0V/+3.3V Low Power Microprocessor
Supervisory Circuits
s Precision Low Voltage Monitor:
SP706P/R and SP708R at +2.63V
SP706S and SP708S at +2.93V
SP706T and SP708T at +3.08V
s RESET Pulse Width - 200ms
s Independent Watchdog Timer - 1.6 sec
Timeout (SP706P/S/R/T)
s 40µA Maximum Supply Current
s Debounced TTL/CMOS Manual-Reset Input
s RESET Asserted Down to VCC = 1V
s RESET Output:
SP706P Active-High
SP706R/S/T Active-Low
SP708R/S/T Both Active High + Active Low
s WDI Can Be Left Floating, Disabling the
Watchdog Function
DESCRIPTION
s Built-In Vcc Glitch Immunity
s Available in 8-pin PDIP, NSOIC, and
µSOIC packages
s Voltage Monitor for Power Failure or Low
Battery Warning
s Pin Compatible Enhancement to Industry
Standards 706P/R/S/T and 708R/S/T
The SP706P/S/R/T, SP708R/S/T series is a family of microprocessor (µP) supervisory circuits
that integrate myriad components involved in discrete solutions which monitor power-supply and
battery, in µP, and digital systems. The SP706P/S/R/T, SP708R/S/T series will significantly
improve system reliability and operational efficiency when compared to results obtained with
discrete components. The features of the SP706P/S/R/T, SP708R/S/T series include a
watchdog timer, a µP reset, a Power Fail Comparator, and a manual-reset input. The SP706P/
S/R/T, SP708R/S/T series is ideal for +3.0V or +3.3V applications in automotive systems,
computers, controllers, and intelligent instruments. The SP706P/S/R/T, SP708R/S/T series is
an ideal solution for systems in which critical monitoring of the power supply to the µP and related
digital components is demanded.
Part Number RESET Active RESET Threshold Manual Reset PFI Accuracy Watchdog Input
SP706P
HIGH
2.63V
YES
4%
YES
SP706R
LOW
2.63V
YES
4%
YES
SP706S
LOW
2.93V
YES
4%
YES
SP706T
LOW
3.08V
YES
4%
YES
SP708R
LOW/HIGH
2.63V
YES
4%
NO
SP708S
LOW/HIGH
2.93V
YES
4%
NO
SP708T
LOW/HIGH
3.08V
YES
4%
NO
Rev. 10-17-00
SP706 +3.0/ +3.3 Low Power Microprocessor Circuits
1
© Copyright 2000 Sipex Corporation
1 page  
PIN DESCRIPTION
NAME
FUNCTION
Manual Reset - This input triggers a reset pulse
when pulled below 0.8V. This active-LOW input
MR has an internal 70µA pull-up current. It can be
driven from a TTL or CMOS logic line or shorted
to ground with a switch
SP706P SP706R/S/T SP708R/S/T
DIP/
SOIC
µSOIC
DIP/
SOIC
µSOIC
DIP/
SOIC
µSOIC
13 13 1 3
VCC
GND
Voltage input.
Ground reference for all signals
24242 4
35353 5
Power-Fail Input - When this voltage monitor input
PFI is less than 1.25V, PFO goes LOW. Connect PFI 4 6 4 6 4 6
to ground or VCC when not in use.
PFO
Power-Fail Output - This output is HIGH until PFI
is less than 1.25V.
5
7
5
7
5
7
Watchdog Input - If this input remains HIGH or
LOW for 1.6s, the internal watchdog timer times
out and WDO goes LOW. Floating WDI or
WDI
connecting WDI to a high-impedance tri-state
buffer disables the watchdog feature. The internal
6
8
6
8
-
watchdog timer clears whenever RESET is
asserted, WDI is tri-stated, or whenever WDI sees
a rising or falling edge.
-
N.C. No Connect.
-- - -68
Active-LOW RESET Output - This output pulses
LOW for 200ms when triggered and stays LOW
whenever VCC is below the reset threshold. It
RESET remains LOW for 200ms after Vcc rises above the
-
-
7
17
1
reset threshold or MR goes from LOW to HIGH.
A watchdog timeout will not trigger RESET unless
WDO is connected to MR.
Watchdog Output - This output pulls LOW when
the internal watchdog timer finishes its 1.6s count
and does not go HIGH again until the watchdog is
cleared. WDO also goes LOW during low-line
WDO
conditions. Whenever VCC is below the reset
threshold, WDO stays LOW. However, unlike
8282 -
RESET, WDO does not have a minimum pulse
width. As soon as VCC is above the reset
threshold, WDO goes HIGH with no delay.
-
Active-HIGH RESET Output - This output is the
RESET
complement of RESET. Whenever RESET is
HIGH, RESET is LOW, and vice versa. Note the
7
1
-
-
8
2
SP708R/S/T has a reset output only.
Table 1. Device Pin Description
Rev. 10-17-00
SP706 +3.0/ +3.3 Low Power Microprocessor Circuits
5
© Copyright 2000 Sipex Corporation
5 Page 
tWP
+3.3V
WDI 0V
+3.3V
WDO 0V
+3.3V
RESET*
0V
+3.3V
RESET* 0V
tWD tWD
tWD
tRS
* externally triggered LOW by MR,
RESET is for the SP813L/813M only
Figure 14. Watchdog Timing Waveforms
To build an early-warning circuit for power
failure, connect the PFI pin to a voltage divider
as shown in Figure 16. Choose the voltage
divider ratio so that the voltage at PFI falls
below 1.25V just before the +5V regulator drops
out. Use PFO to interrupt the µP so it can prepare
for an orderly power-down.
Manual Reset
The manual-reset input (MR) allows RESET to
be triggered by a pushbutton switch. The switch
is effectively debounced by the 140ms
minimum RESET pulse width. MR is TTL/
CMOS logic compatible, so it can be driven by
an external logic line. MR can be used to force
a watchdog timeout to generate a RESET pulse
in the SP706P/R/S/T-SP708R/S/T series.
Simply connect WDO to MR.
VCC
+3.3V
0V
VRT
VRT
WDO
+3.3V
0V
+3.3V
RESET
0V
tRS tRS
MR*
+3.3V
0V
*externally driven LOW
tMD
tMR
Figure 15. Timing Diagrams with WDI Tri-stated. The RESET Output is the Inverse of the RESET Waveform
Shown.
Rev. 10-17-00
SP706 +3.0/ +3.3 Low Power Microprocessor Circuits
11
© Copyright 2000 Sipex Corporation
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet SP706R.PDF ] | |
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