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PDF PIC16LF870 Data sheet ( Hoja de datos )
| Número de pieza | PIC16LF870 | |
| Descripción | (PIC16LF871) 28/40-Pin 8-Bit CMOS FLASH Microcontrollers | |
| Fabricantes | Microchip | |
| Logotipo |  |
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PIC16F870/871
28/40-Pin 8-Bit CMOS FLASH Microcontrollers
Devices Included in this Data Sheet:
• PIC16F870
• PIC16F871
Microcontroller Core Features:
• High-performance RISC CPU
• Only 35 single word instructions to learn
• All single cycle instructions except for program
branches which are two cycle
• Operating speed: DC - 20 MHz clock input
DC - 200 ns instruction cycle
• 2K x 14 words of FLASH Program Memory
128 x 8 bytes of Data Memory (RAM)
64 x 8 bytes of EEPROM Data Memory
• Pinout compatible to the PIC16CXXX 28 and 40-
pin devices
• Interrupt capability (up to 11 sources)
• Eight level deep hardware stack
• Direct, indirect and relative addressing modes
• Power-on Reset (POR)
• Power-up Timer (PWRT) and
Oscillator Start-up Timer (OST)
• Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
• Programmable code-protection
• Power saving SLEEP mode
• Selectable oscillator options
• Low-power, high-speed CMOS FLASH/EEPROM
technology
• Fully static design
• In-Circuit Serial Programming™ (ICSP) via two
pins
• Single 5V In-Circuit Serial Programming capability
• In-Circuit Debugging via two pins
• Processor read/write access to program memory
• Wide operating voltage range: 2.0V to 5.5V
• High Sink/Source Current: 25 mA
• Commercial and Industrial temperature ranges
• Low-power consumption:
- < 1.6 mA typical @ 5V, 4 MHz
- 20 µA typical @ 3V, 32 kHz
- < 1 µA typical standby current
Pin Diagram
PDIP
MCLR/VPP/THV
RA0/AN0
RA1/AN1
RA2/AN2/VREF-
RA3/AN3/VREF+
RA4/T0CKI
RA5/AN4
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
VDD
VSS
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
RC1/T1OSI
RC2/CCP1
RC3
RD0/PSP0
RD1/PSP1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40 RB7/PGD
39 RB6/PGC
38 RB5
37 RB4
36 RB3/PGM
35 RB2
34 RB1
33 RB0/INT
32 VDD
31 VSS
30 RD7/PSP7
29 RD6/PSP6
28 RD5/PSP5
27 RD4/PSP4
26 RC7/RX/DT
25 RC6/TX/CK
24 RC5
23 RC4
22 RD3/PSP3
21 RD2/PSP2
Peripheral Features:
• Timer0: 8-bit timer/counter with 8-bit prescaler
• Timer1: 16-bit timer/counter with prescaler,
can be incremented during sleep via external
crystal/clock
• Timer2: 8-bit timer/counter with 8-bit period
register, prescaler and postscaler
• One Capture, Compare, PWM module
- Capture is 16-bit, max. resolution is 12.5 ns
- Compare is 16-bit, max. resolution is 200 ns
- PWM max. resolution is 10-bit
• 10-bit multi-channel Analog-to-Digital converter
• Universal Synchronous Asynchronous Receiver
Transmitter (USART/SCI) with 9-bit address
detection
• Parallel Slave Port (PSP) 8-bits wide, with
external RD, WR and CS controls (40/44-pin only)
• Brown-out detection circuitry for
Brown-out Reset (BOR)
© 1999 Microchip Technology Inc.
Preliminary
DS30569A-page 1
1 page  
PIC16F870/871
1.0 DEVICE OVERVIEW
This document contains device-specific information.
Additional information may be found in the PICmicro™
Mid-Range Reference Manual, (DS33023), which may
be obtained from your local Microchip Sales Represen-
tative or downloaded from the Microchip website. The
Reference Manual should be considered a comple-
mentary document to this data sheet, and is highly rec-
ommended reading for a better understanding of the
device architecture and operation of the peripheral
modules.
FIGURE 1-1:
Device
PIC16F870
PIC16F870 BLOCK DIAGRAM
Program
FLASH
2K
Data Memory
128 Bytes
Data
EEPROM
64 Bytes
There are two devices (PIC16F870 and PIC16F871)
covered by this data sheet. The PIC16F870 device
comes in a 28-pin package and the PIC16F871 device
comes in a 40-pin package. The 28-pin device does not
have a Parallel Slave Port implemented.
The following two figures are device block diagrams
sorted by pin number; 28-pin for Figure 1-1 and 40-pin
for Figure 1-2. The 28-pin and 40-pin pinouts are listed
in Table 1-1 and Table 1-2, respectively.
FLASH
Program
Memory
13
Program Counter
8 Level Stack
(13-bit)
Data Bus
8
RAM
File
Registers
Program
Bus
14
Instruction reg
RAM Addr (1) 9
Addr MUX
Direct Addr 7
Indirect
8 Addr
FSR reg
STATUS reg
8
Instruction
Decode &
Control
OSC1/CLKIN
OSC2/CLKOUT
Timing
Generation
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
In-Circuit
Debugger
Low-Voltage
Programming
3 MUX
ALU
8
W reg
PORTA
PORTB
PORTC
RA0/AN0
RA1/AN1
RA2/AN2/VREF-
RA3/AN3/VREF+
RA4/T0CKI
RA5/AN4
RB0/INT
RB1
RB2
RB3/PGM
RB4
RB5
RB6/PGC
RB7/PGD
RC0/T1OSO/T1CKI
RC1/T1OSI
RC2/CCP1
RC3
RC4
RC5
RC6/TX/CK
RC7/RX/DT
Timer0
Timer1
MCLR VDD, VSS
Timer2
10-bit A/D
Data EEPROM
CCP1
Note 1: Higher order bits are from the STATUS register.
USART
© 1999 Microchip Technology Inc.
Preliminary
DS30569A-page 5
5 Page 
2.0 MEMORY ORGANIZATION
There are three memory blocks in each of these
PICmicro® MCUs. The Program Memory and Data
Memory have separate buses, so that concurrent
access can occur, and is detailed in this section. The
EEPROM data memory block is detailed in
Section 4.0.
Additional information on device memory may be found
in the PICmicro™ Mid-Range Reference Manual,
(DS33023).
2.1 Program Memory Organization
The PIC16F870/871 devices have a 13-bit program
counter capable of addressing an 8K x 14 program
memory space. The PIC16F870/871 devices have 2K
x 14 words of FLASH program memory. Accessing a
location above the physically implemented address will
cause a wraparound.
The reset vector is at 0000h and the interrupt vector is
at 0004h.
FIGURE 2-1: PIC16F870/871 PROGRAM
MEMORY MAP AND STACK
PC<12:0>
CALL, RETURN
RETFIE, RETLW
13
Stack Level 1
Stack Level 2
Stack Level 8
Reset Vector
0000h
PIC16F870/871
2.2 Data Memory Organization
The data memory is partitioned into multiple banks
which contain the General Purpose Registers and the
Special Function Registers. Bits RP1(STATUS<6>) and
RP0 (STATUS<5>) are the bank select bits.
RP<1:0>
00
Bank
0
01 1
10 2
11 3
Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the Special
Function Registers. Above the Special Function Regis-
ters are General Purpose Registers, implemented as
static RAM. All implemented banks contain Special
Function Registers. Some “high use” Special Function
Registers from one bank may be mirrored in another
bank for code reduction and quicker access.
Note: EEPROM Data Memory description can be
found in Section 4.0 of this Data Sheet
2.2.1 GENERAL PURPOSE REGISTER FILE
The register file can be accessed either directly, or indi-
rectly through the File Select Register FSR.
On-Chip
Program
Memory
Interrupt Vector
Page 0
0004h
0005h
07FFh
0800h
1FFFh
© 1999 Microchip Technology Inc.
Preliminary
DS30569A-page 11
11 Page | ||
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