PDF PPC405CR Data sheet ( Hoja de datos )

Número de pieza	PPC405CR
Descripción	Power PC 405CR Embedded Processor
Fabricantes	Applied Micro Circuits
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No Preview Available ! Part Number PPC405CR Revision 1.02 – January 11, 2005 PPC405CR PowerPC 405CR Embedded Processor Data Sheet Features • PowerPC® 405 32-bit RISC processor core operating up to 266MHz - Memory Management Unit - 16KB instruction and 8KB data caches - Multiply-Accumulate (MAC) function, including fast multiply unit - Programmable Timers • Synchronous DRAM (SDRAM) interface oper- ating up to 133MHz - 32-bit interface for non-ECC applications - 40-bit interface serves 32 bits of data plus 8 check bits for ECC applications • External Peripheral Bus - Flash ROM/Boot ROM interface - Direct support for 8-, 16-, or 32-bit SRAM and external peripherals - Up to eight devices - External Mastering supported • DMA support for external peripherals, internal UART and memory - Scatter-gather chaining supported - Four channels • Programmable Interrupt Controller supports interrupts from a variety of sources - Supports 7 external and 10 internal interrupts - Edge triggered or level-sensitive - Positive or negative active - Non-critical or critical interrupt to processor core - Programmable critical interrupt priority ordering • Two serial ports (16550 compatible UART) • One IIC interface • General Purpose I/O (GPIO) available • Supports JTAG for board level testing • Internal Processor Local Bus (PLB) runs at SDRAM interface frequency Description The PowerPC 405CR (PPC405CR) is a 32-bit RISC embedded controller. High performance, peripheral integration, and low cost make the device ideal for wired communications, network printers, and other computing applications. This device is an easy upgrade for systems based on PowerPC 403xx embedded processors, while provid- ing a base for custom chip designs. The controller is powered by a PPC405 embedded core. This core tightly couples a 266 MHz CPU, MMU, instruction and data caches, and debug logic. Fine- tuning of the core reduces data transfer overhead, minimizes pipeline stalls, and improves performance. The PPC405CR employs the IBM CoreConnect™ bus architecture. This architecture, as implemented on the PPC405CR, consists of a 64-bit, 133-MHz Processor Local Bus (PLB) and a 32-bit, 66-MHz On-Chip Peripheral Bus (OPB). High-performance peripherals attach to the PLB and less performance-critical periph- erals attach to the OPB. Technology: CMOS SA-12E 0.25 µm (0.18 µm Leff) Package: 27mm, 316-ball enhanced plastic ball grid array (E-PBGA) Power (estimated): Typical 0.8 W, Maximum 2.0 W at 200 MHz. AMCC 1 1 page PPC405CR – PowerPC 405CR Embedded Processor Revision 1.02 – January 11, 2005 Data Sheet Figure 1. PPC405CR Embedded Controller Functional Block Diagram Universal Interrupt Controller 8KB D-Cache Clock Control Reset Power Mgmt Timers MMU PPC405 Processor Core JTAG DCU Trace ICU DCRs DCR Bus GPIO IIC UART UART 16KB Arb I-Cache On-chip Peripheral Bus (OPB) CoDnMtroAller (4-Channel) OPB Bridge Arb Processor Local Bus (PLB) Code Decompression (CodePack™) SDRAM Controller External Bus Controller External Bus Master Controller 13-bit addr 32-bit data 32-bit addr 32-bit data The PPC405CR is designed using the IBM Microelectronics Blue Logic® methodology in which major functional blocks are integrated together to create an application-specific ASIC product. This approach provides a consistent way to create complex ASICs using IBM CoreConnect™ Bus Architecture. AMCC 5 5 Page PPC405CR – PowerPC 405CR Embedded Processor Revision 1.02 – January 11, 2005 Data Sheet Pin Lists In this section there are two tables that correlate the external signals to the physical package pin (ball) on which they appear. The following table lists all the external signals in alphabetical order and shows the ball number on which the signal appears. Multiplexed signals are shown with the default signal (following reset) not in brackets and the alternate signal in brackets. The page number listed gives the page in “Signal Functional Description” on page 23 where the signals in the indicated interface group begin. Table 3. Signals Listed Alphabetically (Sheet 1 of 7) Signal Name AVDD BA0 BA1 BankSel0 BankSel1 BankSel2 BankSel3 BusReq CAS ClkEn0 ClkEn1 DMAAck0 DMAAck1 DMAAck2 DMAAck3 DMAReq0 DMAReq1 DMAReq2 DMAReq3 DQM0 DQM1 DQM2 DQM3 DQMCB DrvrInh1 DrvrInh2 ECC0 ECC1 ECC2 ECC3 ECC4 ECC5 ECC6 ECC7 EOT0/TC0 EOT1/TC1 EOT2/TC2 EOT3/TC3 ExtAck ExtReq ExtReset Ball E20 J17 H18 L19 N17 P17 U19 P2 K17 J19 G20 C16 B17 B16 A14 A19 C15 B15 A8 U18 W14 Y10 U8 V19 F17 C19 V17 Y18 U14 V13 Y13 V12 W11 V11 G4 F2 W1 Y2 U5 Y3 P4 Power SDRAM Interface Group SDRAM External Master Peripheral SDRAM SDRAM External Slave Peripheral External Slave Peripheral SDRAM SDRAM System SDRAM External Slave Peripheral External Master Peripheral Page 27 23 23 25 23 23 23 23 23 23 26 23 23 25 AMCC 11 11 Page

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