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PDF MN89302 Data sheet ( Hoja de datos )
| Número de pieza | MN89302 | |
| Descripción | SVGA Display Controller | |
| Fabricantes | Panasonic | |
| Logotipo |  |
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For Information Equipment
MN89302
SVGA Display Controller
Overview
The MN89302 is an LCD/CRT display controller with
IBM™ VGA-compatible registers. It features all the neces-
sary interfaces for a compact display system: ISA bus inter-
face, local bus interface, DRAM interface, and LCD panel
interface. The built-in graphics acceleration functions include
support for bit-block transfers (BITBLT) and hardware cursor.
Note: IBM™ and VGA are registered trademarks of International
Business Machines Corporation.
Features
Monochrome STN LCD panel support
Maximum display size: 800 × 600
Support for single and dual panels
32-monochrome gradation
Color STN LCD panel support
Maximum display size: 800 × 600
Support for single and dual panels
32-gradation for each color (RGB)
Color TFT LCD panel support
Maximum display size: 800 × 600
5-bit output for red and blue; 6-bit output for green
Maximum number of colors in concurrent display
320 × 240: 64k (TFT, STN)
640 × 480: 256/260K palette (TFT, STN)
800 × 600: 256/260K palette (TFT, STN)
Built-in graphics acceleration functions
• Bit-block transfers (BITBLT) to and from
host video memory and within video memory
• Hardware cursor (16 × 16 or 32 × 32)
Built-in automatic display centering
Built-in gradation control table (rewritable) for
optimizing gradation to match panel
DRAM interface with 16-bit bus
• Support for 2CAS/2WE mode
• Refresh control
Host interfaces
• ISA bus (16-bit)
• i386/i486 local bus (16-bit)
Note: i386 and i486 are trademarks of Intel Corporation.
Applications
Point-of-sale terminals, Factory automation terminals,
word processors, and other terminals
1 page  
For Information Equipment
MN89302
Pin Descriptions (continued)
Pin No. Symbol
I/O
94 LCAS
O
Level
CMOS
92 WE
O CMOS
112 to 97 MD[15:0]
26 BIOSEN
49 BACKON
I/O TTL
O CMOS
O CMOS
50 LCDON
O CMOS
51 LOGICON O CMOS
56 LP
O CMOS
55 FP
O CMOS
54 DISP
O CMOS
57 DCLK
O CMOS
77 to 70
67 to 60
UD[7:0]
LD[7:0]
O CMOS
O CMOS
Function Description
Lower Column Address Strobe (LCAS)
This output is the strobe signal for the lower column address
latch. In the 2WE mode, however, it functions as the LWE
signal.
Write Enable
This output is the data write signal. In the 2WE mode, however,
it functions as the UWE signal.
Memory Data
These pins represent the data bus to the DRAM.
BIOS Enable
This output enables ROM BIOS output.
Backlight ON
This output requests backlighting.
"L" level: OFF; "H" level: ON
LCD Drive ON
This output requests power-ON for the LCD panel.
"L" level: OFF; "H" level: ON
LCD Logic ON
This output requests power-ON for LCD panel logic circuits.
"L" level: OFF; "H" level: ON
Line Pulse
This output provides pulses indicating the end of a line of the
LCD panel.
Frame Pulse
This output provides pulses indicating the start of a frame of the
LCD panel.
Display Enable
This output enables the LCD display. An external RAMDAC
uses this signal as a blanking signal. A TFT LCD uses it as an
enable signal.
Data Shift Clock
This pin provides a data shift clock signal for an STN LCD panel
or a dot clock signal for a TFT LCD panel or external RAMDAC.
Upper Data[7:0]
Lower Data[7:0]
This pins provide display data. Usage varies with the LCD panel
type.
5 Page 
For Information Equipment
Package Dimensions (Unit: mm)
QFH128-P-1818
20.0±0.2
18.0±0.2
96
97
65
64
MN89302
128
1
(1.25)
33
32
0.5 0.2±0.1
1.0±0.2
0.1 SEATING PLANE
0.5±0.2
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet MN89302.PDF ] | |
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