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PDF MN838850 Data sheet ( Hoja de datos )
| Número de pieza | MN838850 | |
| Descripción | Source Driver for LCD Panel Drive | |
| Fabricantes | Panasonic | |
| Logotipo |  |
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Color TFT LCD Driver
MN838850
Source Driver for LCD Panel Drive
s Overview
The MN838850 converts digital display data from a personal computer or an engineering workstation to analog signal
voltages to allow those signals to be displayed on a color TFT LCD panel.
s Features
• Includes a built-in D/A converter and accepts 8-bit digital input data for 16.7-million color display.
• Output dynamic range: 14.6 V P-P (when AVDD = 15 V)
• Supports both dot inversion drive and source inversion drive schemes.
• Number of drive outputs: 384
• Input data bus: acquires two pixels at the same time
• Supports control of data inversion at each clock cycle.
• Supports γ correction.
• Adopts a drive scheme that does not require precharging.
• Allows serial cascade connection.
• The clock is automatically stopped after the acquisition of a fixed amount of data.
• The shift register shift direction can be set to be either left-to-right or right-to-left.
• Digital circuit block features low-voltage operation:
2.7 to 3.6 V
• Maximum operating clock frequency:
50 MHz (3.1 to 3.6 V), 40 MHz (2.7 to 3.6 V)
s Applications
• TFT LCD panels
1
1 page  
Color TFT LCD Driver
MN838850
s Functional Description
• Relationship between the data input and the analog output pins
The input mode used by this IC is a two-pixel mode in which the data for two pixels is input in parallel from the D0(7:0),
D1(7:0), D2(7:0), D3(7:0), D4(7:0), and D5(7:0) input ports.
The correspondence between the data input ports and the output pins is as follows.
Y(6n−5) = D00 to D07
Y(6n−2) = D30 to D37
Y(6n−4) = D10 to D17
Y(6n−1) = D40 to D47
Y(6n−3) = D20 to D27
Y(6n) = D50 to D57 (n = 1, 2, ······, 64)
Figure 1 shows an example of color data and pin connections when RL is high.
This example shows the case where the pixels are in the order R, B, G starting at the left edge of the LCD panel.
R2n-1 D00 to D07
D10 to D17
B2n-1
D20 to D27
G2n-1
D30 to D37
R2n
D40 to D47
B2n
G2n D50 to D57
(n=1..)
MN838850
············
R1 B1 G1 R2 B2 G2 R3 B3 G3 R4 ···
R1 B1 G1 R2 B2 G2 R3 B3 G3 R4 ···
R1 B1 G1 R2 B2 G2 R3 B3 G3 R4 ···
FY
D0(7 : 0)
D1(7 : 0)
D2(7 : 0)
D3(7 : 0)
D4(7 : 0)
D5(7 : 0)
LCD Panel
R1 R3 R5 R7 R9 R11 R13 R15 R17 R19 R21 R23 R25 R27
B1 B3 B5 B7 B9 B11 B13 B15 B17 B19 B21 B23 B25 B27
G1 G3 G5 G7 G9 G11 G13 G15 G17 G19 G21 G23 G25 G27
R2 R4 R6 R8 R10 R12 R14 R16 R18 R20 R22 R24 R26 R28
B2 B4 B6 B8 B10 B12 B14 B16 B18 B20 B22 B24 B26 B28
G2 G4 G6 G8 G10 G12 G14 G16 G18 G20 G22 G24 G26 G28
Figure 1 Relationship between Input and Output Pins (When RL is high and the shift direction is Y1 to Y384)
5
5 Page 
Color TFT LCD Driver
MN838850
s Functional Description (continued)
• Relationship between input data values and output voltages (continued)
Apply the voltages for the γ correction to the pins VREF0 to VREF9.
The γ correction voltage input pins are divided into two groups: the high-level output control group and the low-level
output control group, and each group is connected in series with resistors. Each of these resistor series has a total
typical value of 14 kΩ.
This structure is shown in the figure. The typical values of the resistors are shown in parentheses.
Note that since these voltages are resistor divided internally, the voltages applied to the VREF pins should be applied
through a low-impedance circuit. If the voltages are directly applied by the resistor divider, the desired output voltages
may not result.
VREF9
VREF8
IC internal circuits
R0 (2000 Ω)
Data correspondence
High-level FF
output side
VREF7
R1 (3800 Ω)
VREF6
R2 (4500 Ω)
VREF5
VREF4
VREF3
R3 (3700 Ω)
R4 (3700 Ω)
00
Low-level 00
output side
VREF2
R5 (4500 Ω)
VREF1
R6 (3800 Ω)
VREF0
R7 (2000 Ω)
FF
11
11 Page | ||
| Páginas | Total 26 Páginas | |
| PDF Descargar | [ Datasheet MN838850.PDF ] | |
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