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PDF PI74FCT2543T Data sheet ( Hoja de datos )

Número de pieza PI74FCT2543T
Descripción Fast CMOS Latch Transceivers
Fabricantes Pericom Semiconductor 
Logotipo Pericom Semiconductor Logotipo



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No Preview Available ! PI74FCT2543T Hoja de datos, Descripción, Manual

PI74FCT543T/544T
(25Series) PI74FCT2543T
(25SerPieIs7)4PFIC7T4F54C3TT2/554434TTLatched Transceivers1122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566778899001122
1122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566778899001122
Fast CMOS
Latched Transceivers
Product Features
• PI74FCT543T/544/2543T is pin compatible with bipolar
FAST™ Series at a higher speed and lower power
consumption
• 25series resistor on all outputs
• TTL input and output levels
• Low ground bounce outputs
• Extremely low static power
• Hysteresis on all inputs
• Industrial operating temperature range: –40°C to +85°C
• Packages available:
– 24-pin 300 mil wide plastic DIP (P)
– 24-pin 150 mil wide plastic QSOP (Q)
– 24-pin 150 mil wide plastic TQSOP (R)
– 24-pin 300 mil wide plastic SOIC (S)
• Device models available on request
PI74FCT543/544/2543T Logic Block Diagram
Product Description
Pericom Semiconductor’s PI74FCT series of logic circuits are
produced using the Company’s advanced 0.8 micron CMOS
technology, achieving industry leading speed grades. All
PI74FCT2XXX devices have a built-in 25 ohm series resistor on all
outputs to reduce noise because of reflections, thus eliminating the
need for an external terminating resistor.
The PI74FCT543T/544T and PI74FCT2543T is an 8-bit wide non-
inverting transceiver designed with two sets of eight D-type latches
with separate input and output controls for each set. For data flow
from A to B, for example, the A-to-B Enable (CEAB) input must be
LOW in order to enter data from A0–A7 or to take data from B0–B7,
as indicated in the Truth Table. With CEAB LOW, a LOW signal
makes the A-to-B latches transparent; a subsequent LOW-to-HIGH
transition of the LEAB signal puts the A latches in the storage mode
and their outputs no longer change the A inputs. With CEAB and
OEAB both LOW, the 3-state B output buffers are active and reflect
the data present at the output of the A latches. Control of data from
B to A is similar, but uses the CEAB, LEAB, and OEAB inputs. The
PI74FCT543T is a non-inverting of the PI74FCT544T.
A0
A1
A2
A3
A4
A5
A6
A7
OEBA
CEBA
LEBA
DQ
LE
DETAIL A
QD
LE
DETAIL A x 7
B0
B1
B2
B3
B4
B5
B6
B7
NOTE: PI74FCT543/2543T function is shown.
1
OEAB
CEAB
LEAB
PS2020A 03/11/96

1 page




PI74FCT2543T pdf
PI74FCT543T/544T
(25Series) PI74FCT2543T
Latched Transceivers1122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566778899001122
PI74FCT543/2543T (non-inverting) Switching Characteristics over Operating Range
Parameters Description
Conditions(1)
tPLH Propagation Delay Transparent CL = 50 pF
tPHL Mode AN to BN or BN to AN
RL = 500
tPLH Propagation Delay
tPHL LEBA to AN, LEAB to BN
tPZH Output Enable Time
tPZL OEBA or OEAB to AN or BN
CEBA or CEAB to AN or BN
tPZH Output Disable Time(3)
tPZL OEBA or OEAB to AN or BN
CEBA or CEAB to AN or BN
tSU Setup Time, HIGH or LOW
AN or BN to LEBA or LEAB
tH Hold Time, HIGH or LOW
AN or BN to LEBA or LEAB
tW LEBA or LEAB Pulse Width LOW(3)
543T/2543T
Com.
Min Max
2.5 8.5
2.5 12.5
2.0 12.0
2.0 9.0
3.0 —
2.0 —
5.0 —
543AT/2543AT
Com.
Min Max
2.5 6.5
2.5 8.0
2.0 9.0
2.0 7.5
2.0 —
2.0 —
5.0 —
543CT/2543CT
Com.
Min Max
2.5 5.3
2.5 7.0
2.0 8.0
2.0 6.5
2.0 —
2.0 —
5.0 —
543DT
Com.
Min Max
2.5 4.4
Unit
ns
2.5 5.0 ns
2.0 5.4 ns
2.0 4.3 ns
1.5 — ns
1.5 — ns
3.0 — ns
PI74FCT544T (inverting) Switching Characteristics over Operating Range
Parameters Description
Conditions(1)
tPLH Propagation Delay Transparent CL = 50 pF
tPHL Mode AN to BN or BN to AN
RL = 500
tPLH Propagation Delay
tPHL LEBA to AN, LEAB to BN
tPZH Output Enable Time
tPZL OEBA or OEAB to AN or BN
CEBA or CEAB to AN or BN
tPZH Output Disable Time(3)
tPZL OEBA or OEAB to AN or BN
CEBA or CEAB to AN or BN
tSU Setup Time, HIGH or LOW
AN or BN to LEBA or LEAB
tH Hold Time, HIGH or LOW
AN or BN to LEBA or LEAB
tW LEBA or LEAB Pulse Width LOW(3)
544T
Com.
Min Max
2.5 8.5
2.5 12.5
2.0 12.0
2.0 9.0
3.0 —
2.0 —
5.0 —
544AT
Com.
Min Max
2.5 6.5
2.5 8.0
2.0 9.0
2.0 7.5
2.0 —
2.0 —
5.0 —
544CT
Com.
Min Max
2.5 5.3
2.5 7.0
2.0 8.0
2.0 6.5
2.0 —
2.0 —
5.0 —
Notes:
1. See test circuit and wave forms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter is guaranteed but not production tested.
Unit
ns
ns
ns
ns
ns
ns
ns
Pericom Semiconductor Corporation
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com
5 PS2020A 03/11/96

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