PDF BT261 Data sheet ( Hoja de datos )

Número de pieza	BT261
Descripción	30 Mhz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller
Fabricantes	Brooktree
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No Preview Available ! Bt261 30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller The Bt261 HSYNC Line Lock Controller is designed speciﬁcally for image cap- ture applications. Either composite video or TTL composite sync information is input via VIDEO. An internal sync separator separates horizontal and vertical sync infor- mation. Programmable horizontal and vertical video timing enables recovery of both standard and nonstandard timing information. An external VCO may be used in conjunction with the on-chip phase com- parator for implementation of clocks locked to the horizontal frequency. Alternately, a high-speed clock (OSC) may be divided down to generate the pixel clock. The phase of the generated pixel clock is adjusted to align with the noise-gated CSYNC. The higher the OSC clock rate, the lower the pixel clock jitter (the maximum being one half the OSC clock period). The OSC inputs may be conﬁgured to be either TTL or ECL compatible. Thus, four TTL clocks, two TTL clocks and one differential ECL clock, or two differential ECL clocks may be used. The ECL clock inputs are designed to be driven by 10KH ECL using a single +5 V supply. The CLAMP and ZERO outputs are programmed by the MPU to DC restore the video signal and to zero the Image Digitizer or A/D converter at the appro- priate time. Functional Block Diagram Distinguishing Features • Programmable 12-bit Video Timing • Bidirectional HSYNC and CLOCK Pins • Horizontal Sync Noise Gating • External VCO Support • Standard MPU Interface • TTL Compatible • + 5 V Monolithic CMOS • 28-pin PLCC Package • Typical Power Dissipation: 300˙mW Applications • Image Processing • Video Digitizing • Desktop Publishing • Graphic Art Systems OSC1 OSC1* OSC2 OSC2* M U X Noise-Gated CSYNC* HSYNC Phase Comparator XTAL OSC to Pixel Clock Generator 3-State Buffer Horizontal Counter VIDEO SYNC Detect SYNC Noise Gate Vertical SYNC Processor Horizontal Video Timing Control D0–D7 RD* WR* A0 PCOUT CLOCK ZERO CLAMP HSYNC CAPTURE VSYNC* FIELD CSYNC* Brooktree® Brooktree Division • Rockwell Semiconductor Systems, Inc. • 9868 Scranton Road • San Diego, CA 92121-3707 619-452-7580 • 1-800-2-BT-APPS • FAX: 619-452-1249 • Internet: [email protected] • L261_H 1 page Bt261 30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller Brooktree® L261_H v 5 Page Bt261 30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller CIRCUIT DESCRIPTION Horizontal Counter Brooktree® Horizontal Counter The rising edge of pixel clock (CLOCK) increments a 12-bit horizontal counter used to generate horizontal video timing information. The value of the counter is compared to various registers to determine when signals are to be asserted (set high) and negated (set low). $000 corresponds to the falling edge of CSYNC. When the part is used with an external high-speed oscillator and divided down to generate the pixel clock, there is no pipeline delay between CSYNC and count zero. However, when the part is used in phase locked loop mode with an external VCO, there is a three-pixel-clock pipeline delay between CSYNC* and count zero. Horizontal Sync Separation The Bt261 separates horizontal sync information from CSYNC* by use of the hor- izontal noise gate register, which derives gated composite sync by removing equal- ization and serration pulses at half-line intervals. Two 12-bit noise gate start and stop registers specify at what horizontal count (with pixel clock resolution) to respectively ignore or accept falling sync transi- tions on CSYNC. The sync noise gating is provided to ﬁlter incorrect horizontal sync information from noisy video signals. The noise gating also serves a second purpose: to ﬁlter serration and equalization pulses at half-line intervals from CSYNC during the vertical retrace interval. This enables steady synchronization of horizontal sync in- formation during vertical retrace intervals. HSYNC Input/Output The HSYNC output may be programmed to be either active high or active low. The start value sets the rising edge and the stop value sets the falling edge of HSYNC relative to count zero of the horizontal counter. The beginning or falling edge of HSYNC is typically programmed to be coincident with the beginning of the noise-gated CSYNC*. The HSYNC output may be three-stated via the command register. HSYNC may also be conﬁgured as an input, enabling external circuitry to generate HSYNC and drive the phase comparator. L261_H 5 11 Page

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