PDF MC68HC912B32 Data sheet ( Hoja de datos )

Número de pieza	MC68HC912B32
Descripción	16-Bit Microcontroller
Fabricantes	Motorola Semiconductors
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No Preview Available ! MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MC68HC912B32TS/D MC68HC912B32 Technical Summary 16-Bit Microcontroller 1 Introduction The MC68HC912B32 microcontroller unit (MCU) is a 16-bit device composed of standard on-chip pe- ripherals including a 16-bit central processing unit (CPU12), 32-Kbyte flash EEPROM, 1-Kbyte RAM, 768-byte EEPROM, an asynchronous serial communications interface (SCI), a serial peripheral inter- face (SPI), an 8-channel timer and 16-bit pulse accumulator, an 8-bit analog-to-digital converter (ADC), a four-channel pulse-width modulator (PWM), and a J1850-compatible byte data link communications module (BDLC). The chip is the first 16-bit microcontroller to include both byte-erasable EEPROM and flash EEPROM on the same device. System resource mapping, clock generation, interrupt control and bus interfacing are managed by the Lite integration module (LIM). The MC68HC912B32 has full 16-bit data paths throughout, however, the multiplexed external bus can operate in an 8-bit narrow mode so single 8-bit wide memory can be interfaced for lower cost systems. 1.1 Features • 16-Bit CPU12 — Upward Compatible with M68HC11 Instruction Set — Interrupt Stacking and Programmer’s Model Identical to M68HC11 — 20-Bit ALU — Instruction Queue — Enhanced Indexed Addressing — Fuzzy Logic Instructions • Multiplexed Bus — Single Chip or Expanded — 16/16 Wide or 16/8 Narrow Modes • Memory — 32-Kbyte Flash EEPROM with 2-Kbyte Erase-Protected Boot Block — 768-B yte EEPROM — 1-Kbyte RAM with Single-Cycle Access for Aligned or Misaligned Read/Write • 8-Channel, 8-Bit Analog-to-Digital Converter • 8-Channel Timer — Each Channel Fully Configurable as Either Input Capture or Output Compare — Simple PWM Mode — Modulo Reset of Timer Counter • 16-Bit Pulse Accumulator — External Event Counting — Gated Time Accumulation • Pulse-Width Modulator — 8-Bit, 4-Channel or 16-Bit, 2-Channel — Separate Control for Each Pulse Width and Duty Cycle This document contains information on a new product. Specifications and information herein are subject to change without notice. © MOTOROLA INC., 1997 M 1 page 1.3 MC68HC912B32 Block Diagram VFP BKGD EXTAL XTAL RESET PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 32-KBYTE FLASH EEPROM 1-KBYTE RAM 768-BYTE EEPROM CPU12 SMODN / TAGHI SINGLE-WIRE BACKGROUND DEBUG MODULE PERIODIC INTERRUPT COP WATCHDOG CLOCK MONITOR BREAK POINTS XIRQ IRQ/VPP R/W LSTRB / TAGLO ECLK IPIPE0 / MODA IPIPE1 / MODB DBE LITE INTEGRATION MODULE (LIM) MULTIPLEXED ADDRESS/DATA BUS DDRA PORT A DDRB PORT B ATD CONVERTER AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 IOC0 IOC1 IOC2 TIMER AND IOC3 PULSE OC7 IOC4 ACCUMULATOR IOC5 IOC6 PAI SCI RxD TxD I/O I/O I/O SDI/MISO SDO/MOSI SPI SCK CS/SS PWM PW0 PW1 PW2 PW3 I/O I/O I/O I/O I/O VRH VRL VDDA VSSA VRH VRL VDDA VSSA PAD0 PAD1 PAD2 PAD3 PAD4 PAD5 PAD6 PAD7 PT0 PT1 PT2 PT3 PT4 PT5 PT6 PT7 PS0 PS1 PS2 PS3 PS4 PS5 PS6 PS7 PP0 PP1 PP2 PP3 PP4 PP5 PP6 PP7 WIDE BUS BDLC I/O DLCRx DLCTx I/O I/O I/O I/O I/O PDLC0 PDLC1 PDLC2 PDLC3 PDLC4 PDLC5 PDLC6 NARROW BUS VDD × 2 VSS × 2 POWER FOR INTERNAL CIRCUITRY VDDX × 2 VSSX × 2 POWER FOR I/O DRIVERS MC68HC912B32 MC68HC912B32TS/D Figure 1 MC68HC912B32 Block Diagram MOTOROLA 5 5 Page 3.3 Signal Descriptions 3.3.1 Crystal Driver and External Clock Input (XTAL, EXTAL) These pins provide the interface for either a crystal or a CMOS compatible clock to control the internal clock generator circuitry. Out of reset the frequency applied to EXTAL is twice the desired E-clock rate. All the device clocks are derived from the EXTAL input frequency. EXTAL MCU XTAL 10 MΩ C 2xE CRYSTAL C Figure 4 Common Crystal Connections COMMON XTAL CONN EXTAL MCU XTAL NC 2xE CMOS-COMPATIBLE EXTERNAL OSCILLATOR Figure 5 External Oscillator Connections EXT EXTAL CONN XTAL is the crystal output. The XTAL pin must be left unterminated when an external CMOS compatible clock input is connected to the EXTAL pin. The XTAL output is normally intended to drive only a crystal. The XTAL output can be buffered with a high-impedance buffer to drive the EXTAL input of another de- vice. In all cases take extra care in the circuit board layout around the oscillator pins. Load capacitances shown in the oscillator circuits include all stray layout capacitances. Refer to Figure 4 and Figure 5 for diagrams of oscillator circuits. 3.3.2 E-Clock Output (ECLK) ECLK is the output connection for the internal bus clock and is used to demultiplex the address and data and is used as a timing reference. ECLK frequency is equal to 1/2 the crystal frequency out of reset. E- clock output can be turned off in single-chip modes to reduce the effects of RFI. In special peripheral mode the E clock is an input to the MCU. All clocks, including the E-clock, are halted when the MCU is in STOP mode. It is possible to configure the MCU to interface to slow external memory. ECLK can be stretched for such accesses. MC68HC912B32 MC68HC912B32TS/D MOTOROLA 11 11 Page

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