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PDF MN662724RPE Data sheet ( Hoja de datos )
| Número de pieza | MN662724RPE | |
| Descripción | Signal Processing LSI for CD Players | |
| Fabricantes | Panasonic | |
| Logotipo |  |
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For Audio Equipment
MN662724RPE
Signal Processing LSI for CD Players
Overview
The MN662724RPE is a CD signal processing LSI that,
on a single chip, combines an optics servo for the CD
player (focus, tracking, and traverse servos), digital sig-
nal processing (EFM demodulation and error correction),
and digital servo processing for the spindle motor.
Features
(Optics servo)
Focus, tracking, and traverse servos
Automatic adjustment functions for FO/TR gain,
FO/TR offset, and FO/TR balance
Built-in D/A converter for drive voltage output
Built-in dropout countermeasures
Anti-shock functions
Built-in track cross counter
(Other)
Built-in playback pitch control function (normal
speed only)(±13%)
Built-in support for jitter-free disc rotation synchro-
nization playback
Oscillator shutdown mode
Power management mode
Operating voltage 4.5 to 5.5V
Applications
CD Players
(Digital signal processing)
Built-in DSL and PLL
Frame synchronization detection, holding, and
insertion
Subcode data processing
Q data CRC check
Built-in Q data register
CIRC error detection and correction
C1 decoder: duplex error correction
C2 decoder: triplex error correction
Built-in 16-K bits of RAM for de-interleaving
Audio data interpolation
Average, hold of previous values
Soft muting
Digital attenuation (256 levels)
Software attenuation (256 levels)
Auto cue detection function
Digital audio interface (EIAJ format)
Two audio data serial interfaces:
One switchable between bit rates of 64 fs and
48 fs; the other fixed at 48 fs.
(Spindle motor servo)
CLV digital servo
Switchable servo gain
1 page  
For Audio Equipment
MN662724RPE
Pins Descriptions (continued)
Pin No. Symbol
38 RFDET
I/O
I
Function Description
RF detection signal input.
"L" level: detected.
39 BDO I Dropout signal input.
"H" level: dropout
40
LDON
O
Laser ON signal output.
"H" level: ON.
41 PLLF2 I/O PLL loop-filter characteristic switching pin.
42
PLAY
O
Play signal output.
"H" level: play.
43
WVEL
O
Double-speed status signal output.
"H" level: double-speed.
44 ARF I RF signal input.
45 IREF I Reference current input pin
46 DRF I DSL bias pin.
47 DSLF I/O DSL loop-filter pin.
48 PLLF I/O PLL loop-filter pin.
49 VCOF I/O VCO loop-filter pin.
50 AVDD2 I Power supply for analog circuits (DSL, PLL, D/A converter output, and A/D
converter).
51 AVSS2 I Ground for analog circuits (DSL, PLL, D/A converter output, and A/D
converter).
52
EFM
O EFM signal output. • EFM output.
or CK384
• Crystal oscillator 16.9344 MHz output.
• 384 fs output from signal processing block. (During
variable-pitch operation, this is the VCO clock.)
Commands permit switching among the above three outputs.
53 PCK O
or DSLB
Clock for PLL or DSL balance output.
fPCK=4.3218MHz
54 TOFS O Tracking offset adjustment output.
55
SUBC
O
Subcode serial output.
56 SBCK I Clock input for subcode serial output.
57 VSS I Ground for oscillator circuit.
58 X1 I Crystal oscillator circuit input pin. f=16.9344MHz, 33.8688MHz
59 X2 O Crystal oscillator circuit output pin. f=16.9344MHz, 33.8688MHz
60 VDD I
61 BYTCK or O
Oscillator circuit power supply.
During default operation, byte clock signal output.
TRVSTOP
During command execution, traverse stop signal output. "H" level: stop mode.
62
CLDCK
O
63
FCLK
O
64 IPFLAG O
Subcode frame clock signal output pin.
Crystal frame clock signal output.
Interpolation flag signal output.
(fCLDCK=7.35kHz)
(fFCLK=7.35kHz)
"H" level: interpolation.
65
FLAG
O
Flag signal output.
66
CLVS
O
Spindle servo phase synchronization signal output. "H" level: CLV.
"L" level: rough servo.
67
CRC
O Subcode CRC check result output.
"H" level: OK. "L" level: no good.
68 DEMPH O
De-emphasis detection signal output. "H" level: on.
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet MN662724RPE.PDF ] | |
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