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PDF LTC1426CMS8 Data sheet ( Hoja de datos )
| Número de pieza | LTC1426CMS8 | |
| Descripción | Micropower Dual 6-Bit PWM DAC | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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FEATURES
s Wide Supply Range: 2.7V ≤ VCC ≤ 5.5V
s Wide Reference Voltage Range: 0V to 5.5V
s Two Interface Modes:
Pulse Mode (Increment Only)
Pushbutton Mode (Increment/Decrement)
s Low Supply Current: 50µA
s 0.2µA Supply Current in Shutdown
s Available in 8-Pin MSOP and SO Packages
s DAC Contents Are Retained in Shutdown
s DACs Power-Up at Midrange
s Low Output Impedance: < 100Ω
s Output Frequency: 5kHz Typ
U
APPLICATIONS
s LCD Contrast and Backlight Brightness Control
s Power Supply Voltage Adjustment
s Battery Charger Voltage and Current Adjustment
s GaAs FET Bias Adjustment
s Trimmer Pot Elimination
LTC1426
Micropower
Dual 6-Bit PWM DAC
DESCRIPTION
The LTC®1426 is a dual micropower 6-bit PWM DAC
featuring versatile PWM outputs and a flexible pushbutton
compatible digital interface. The DAC outputs provide a
PWM signal that swings from 0V to VREF, allowing the full-
scale output to be varied by adjusting the voltage at VREF.
The PWM output frequency is typically 5kHz, easing
output filtering requirements. VCC supply current is typi-
cally 50µA and drops to 0.2µA in shutdown.
The LTC1426 can be controlled using one of two interface
modes: pushbutton and pulse. The LTC1426 automati-
cally configures itself into the appropriate mode at start-
up by monitoring the state of the CLK pins. In pushbutton
mode, the CLK pins can be directly connected to external
pushbuttons to control the DAC output. In pulse mode,
the CLK pins can be connected to CMOS compatible
logic. The DAC outputs initially power up at half scale and
the contents of the internal DAC registers are retained in
shutdown.
The LTC1426 is available in 8-pin MSOP and SO packages.
, LTC and LT are registered trademarks of Linear Technology Corporation.
TYPICAL APPLICATION
Pushbutton Adjustable CCFL/LCD Contrast Generator
UP TO 6mA
LAMP
RP1
47k
UP
DOWN
RP2
47k
RSHDN
1M
SHDN
UP CONTRAST
UP/DOWN 1
CCFL UP/DOWN 2
DOWN
3
4
LTC1426
CLK1 SHDN
CLK2 VCC
GND VREF
PWM1 PWM2
8
7
6
5
R3 R4
5.1k 4.99k
1% 1%
C3
10µF
R1
5V 44.2k
1%
C1
0.1µF
R5
20k
1%
C4
0.1µF
R6
40k
1%
R2
44.2k
1%
C2
1µF
ICCFL = 0µA TO 50µA
HIGH VOLTAGE
ROYER
1 16
CCFL PGND CCFL VSW
2 15
ICCFL
BULB
3 14
DIO LT1182 BAT
C7 1µF
4
CCFL VC
5
AGND
6
SHDN
ROYER
VIN
FBP
13
12
11
7
LCD VC
R7 8
C8 10k LCD PGND
0.68µF
10
FBN
9
LCD VSW
5V
C9
2.2µF
8V TO
28V
+ C10
2.2µF
35V
+ C11
2.2µF
35V
CONSULT THE LT1182 DATA SHEET FOR
DETAILS ON THE HIGH VOLTAGE ROYER
AND LCD CONTRAST CONVERTER SECTIONS
LCD
CONTRAST
CONVERTER
VOUT
NEGATIVE
1426 TA01
LCD CONTRAST
VOUT = –10V TO –30V
1
1 page  
BLOCK DIAGRAM
LATCH
AND
LOGIC
MODE SELECT
0 = PUSHBUTTON MODE
1 = PULSE MODE
CLK1
CLK2
INPUT
CONDITIONING
CONTROL
LOGIC
DEBOUNCE
CIRCUIT
SHDN
POWER-ON
RESET
6-BIT
UP/DOWN
COUNTER
6
6-BIT
UP/DOWN
COUNTER
6
6-BIT
UP
COUNTER
6
OSCILLATOR
COMPARATOR
COMPARATOR
Figure 1. LTC1426 Block Diagram
LTC1426
VREF
DRIVER
PWM1
DRIVER
PWM2
1426 F01
DEFI ITIO S
LSB: The least significant bit or the ideal duty cycle
difference between two successive codes.
LSB = DCMAX/64
DCMAX = The DAC output maximum duty cycle
Resolution: The resolution is the number of DAC output
states (64) that divide the full-scale output duty cycle
range. The resolution does not necessarily imply linearity.
INL: End point integral nonlinearity is the maximum devia-
tion from a straight line passing through the end points of
the DAC transfer curve. The INL error at a given code is
calculated as follows:
INL = (DCOUT – DCIDEAL)/LSB
DCIDEAL = (Code)(LSB)
DCOUT = the DAC output duty cycle measured at the
given number of clocked in pulses.
DNL: Differential nonlinearity is the difference between the
measured duty cycle change and the ideal 1LSB duty cycle
change between any two adjacent codes. The DNL error
between any two codes is calculated as follows:
DNL = (∆DCOUT – LSB)/LSB
∆DCOUT = The measured duty cycle difference between
two adjacent codes.
Full-Scale Error: Full-scale error is the difference between
the ideal and measured DAC output duty cycles with all bits
set to one (Code = 63). The full-scale error is calculated as
follows:
FSE = (DCOUT – DCIDEAL)/LSB
DCIDEAL = DCMAX
APPLICATIONS INFORMATION
Dual 6-Bit PWM DAC
Figure 1 shows a block diagram of the LTC1426. Each
6-bit PWM DAC is guaranteed monotonic and is digitally
adjustable in 64 equal steps, which corresponds from 0%
to 98.5% duty cycle full scale. At power-up, the counters
reset to 100000B and both DAC outputs assume midscale
duty cycle. The PWM outputs have an output impedance
of less than 100Ω. The DAC outputs swing from 0V to the
reference voltage, VREF, which can be biased from 0V to
5.5V. The frequency of the DAC outputs is above 3kHz,
easing output filtering.
In the case of a pure resistive load, the voltage measured
across load RL is given by:
V = (VPWM)RL/(RL + ROUT)
5
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet LTC1426CMS8.PDF ] | |
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