|
|
PDF SAA4970T Data sheet ( Hoja de datos )
| Número de pieza | SAA4970T | |
| Descripción | Economical video processing IC ECOBENDIC | |
| Fabricantes | Philips | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de SAA4970T (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
INTEGRATED CIRCUITS
DATA SHEET
SAA4970T
Economical video processing IC
(ECOBENDIC)
Preliminary specification
File under Integrated Circuits, IC02
1996 Oct 25
1 page  
Philips Semiconductors
Economical video processing IC
(ECOBENDIC)
Preliminary specification
SAA4970T
SYMBOL
YIN3
VDD
VSS
YIN2
YIN1
YIN0
UVIN3
UVIN2
UVIN1
UVIN0
CK2
VSS
CK1
TEST1
XtalO
XtalI
PIN TYPE
41 input
42 supply
43 ground
44 input
45 input
46 input
47 input
48 input
49 input
50 input
51 I/O
52 ground
53 I/O
54 input
55 output
56 input
DESCRIPTION
Y input bus bit 3
digital supply voltage (+5 V)
digital ground (0 V)
Y input bus bit 2
Y input bus bit 1
Y input bus bit 0 (LSB)
UV input bus bit 3 (MSB)
UV input bus bit 2
UV input bus bit 1
UV input bus bit 0 (LSB)
display clock
digital ground (0 V)
acquisition clock
test control
external crystal output (12 MHz)
PLL crystal input (12 MHz)
1996 Oct 25
5
5 Page 
Philips Semiconductors
Economical video processing IC
(ECOBENDIC)
Preliminary specification
SAA4970T
VARIABLE INPUT AND OUTPUT DELAYS
To obtain flexibility, a programmable delay difference
between Y and UV can be made at both input and output.
At the input an almost symmetrical range of Y to UV delay
can be made: −3 to +4 clock pulses.
At the output a range of Y to UV delay from −5 to +2 clock
pulses can be made. When using e.g. scavenge circuitry,
which has an additional external delay, the lower delays in
Y are able to compensate this.
COLOUR REFORMATTING
The reformatter changes the DMSD 4 : 1 : 1 format UV
signals into a sequential 8-bit U and V format according to
the following scheme:
input:
U7, U5, U3, U1, U7, U5...etc.
U6, U4, U2, U0, U6, U4...etc.
V7, V5, V3, V1, V7, V5...etc.
V6, V4, V2, V0, V6, V4...etc.
output:
U7, V7, U7, V7...etc.
U6, V6, U6, V6...etc.
U5, V5, U5, V5...etc.
U4, V4, U4, V4...etc.
U3, V3, U3, V3...etc.
U2, V2, U2, V2...etc.
U1, V1, U1, V1...etc.
U0, V0, U0, V0...etc.
If the master clock frequency in the IC is 27 MHz then the
data rate of the reformatter output is 13.5 MHz.
The signals UVbin and UV8bit, supplied by the
microcontroller interface, select binary/twos complement
mode and 8-bit/7-bit operation.
Economy Controller - Programmable Signal
Positioner (ECO-PSP) control/microcontroller
interface and sync processing
The control/microcontroller interface and sync processing
part is designed as a separate unit called the ECO-PSP.
HORIZONTAL AND ACQUISITION BLOCK
CNT_A is an 8-bit counter, which counts up to
256 positions per acquisition video line. The cycle length
of the counter is determined by either:
an external reset (rising edge of R1) on every line or
an internal reset, generated at a certain value of the
counter itself.
For operation with the internal reset only, a value N in the
‘reset CNT_A’ register will result in an N + 1 length cycle.
The R1 signal, generated by the ECO-PLL, should then be
kept at a constant level. This however has not been
foreseen in the ECO-PLL, so this mode of operation is not
implied.
For operation with the external reset only, the ‘reset
CNT_A’ register must be loaded with a value above the
maximum line length. A value of FFH is suggested.
The VI1 input signal is monitored on its rising edge, with
regard to the CNT_A momentary value. By reading out
MUXA the positions of the edge becomes available for the
microcontroller. If VI1 is the video field pulse, the position
of the active edge within a video line becomes available.
This indicates the interlace situation of the acquisition
video signal. A window for discrimination of undesired VI1
edges is used. This window is made in the vertical
acquisition block.
If a write to ‘SAMPLE AQUI and DISPL’ is done, MUXA will
be loaded with the momentary CNT_A contents.
The PIP input signal is monitored on its edges, with regard
to the CNT_A momentary values. If the PIP interrupt is
enabled, an occurring rising edge will generate acquisition
interrupt. By reading out MUXF and MUXG, the positions
of the rising and falling edges become available for the
microcontroller.
The internal acquisition gate pulses GA1, GA2 and GA3
(routed to CLMP, WE and IE) are set and reset at
selectable CNT_A values. The sets of GA2 and GA3 have
to be enabled by the vertical acquisition block. If the set
and reset registers have equal contents, the signal will
remain reset (reset overruling set).
The internal acquisition horizontal pulse HI is HIGH when
the CNT_A contents are equal to a programmable value in
the HI position register.
1996 Oct 25
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SAA4970T.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| SAA4970T | Economical video processing IC ECOBENDIC | Philips |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |