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PDF RS5C321A Data sheet ( Hoja de datos )

Número de pieza RS5C321A
Descripción ULTRA-COMPACT SERIAL REAL-TIME CLOCK ICs WITH 32.768kHz
Fabricantes RICOH electronics devices division 
Logotipo RICOH electronics devices division Logotipo



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ULTRA-COMPACT SERIAL REAL-TIME CLOCK ICs
WITH 32.768kHz
RS5C321A/B
APPLICATION MANUAL
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ELECTRONIC DEVICES DIVISION
NO.EA-040-9908

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RS5C321A pdf
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URTRA-COMPACT ALARM REAL-TIME
CLOCK ICs WITH 32.768kHz
RS5C321A/B
OUTLINE
The RS5C321A/B are CMOS type real-time clock ICs which are connected to the CPU via three signal lines and
capable of serial transmission of clock and calendar data to the CPU.
The RS5C321A/B can generate 32.768kHz clock pulse controled by register. Driving an oscillation circuit at con-
stant voltage, the circuit presents less fluctuations in frequency and current consumption thank to its minimal volt-
age fluctuations consequently realizes low current consumption (0.6µA at 3V). It also provides an oscillator halt
sensing function for application to data validity at power-on and other occasions. Integrated into an ultra compact
and ultra thin 8pin SSOP (0.65mm pitch), the RS5C321A/B are the optimum choice for equipment requiring small
size and low power consumption.
The RS5C321A and the RS5C321B reads/writes data at falling and rising edge of serial clock respectively.
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FEATURES
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• Time keeping voltage 1.6V to 6.0V
• Lowest supply current 0.6µA TYP. (1.5µA MDAaXta.)Sahte3eVt4U.com
• Connection to the CPU via only three pins: CE, SCLK/SCLK and SIO for addressing and data read/write
• A clock counter (counting hours, minutes, and seconds) and a calendar counter (counting leap years, years,
months, days, and days of the week) in BCD code
• 32.768kHz clock pulse controled by register.
• Oscillator halt sensing to judge internal data validity
• Second digit adjustment by ±30 seconds
• 12-hour or 24-hour time display selectable
• Automatic leap year recognition up to the year 2099
• CMOS logic
• Package: 8pin SSOP (0.65mm pitch)
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RS5C321A arduino
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RS5C321A/B
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FUNCTIONAL DESCRIPTIONS
1. Addressing
A3
00
10
20
30
40
50
60
70
81
91
A1
B1
C1
D1
E1
F1
Address
A2 A1
00
00
01
01
10
10
11
11
00
00
01
01
10
10
11
11
Registers
A0
0 1-second counter
(BANK=0)
D3
S8
Data *1
D2 D1
S4 S2
D0
S1
1 10-second counter
(BANK=0)
—*2
S40
S20
S10
0 1-minute counter
(BANK=0)
M8
M4
M2
M1
1 10-minute counter
(BANK=0)
M40
M20
M10
0 1-hour counter
(BANK=0)
H8
H4
H2
H1
1 10-hour counter
(BANK=0)
P/A, H20
H10
0 Day of the week counter
(BANK=0)
W4
W2
W1
1 Scratch register*8
(BANK=0, 1) Scratch*8 Scratch*8 Scratch*8 Scratch*8
0 1-day counter
(BANK=0)
D8
D4
D2
D1
1 10-day counter
(BANK=0)
1-month counter
0
(BANK=0)
32kHz clock pulse control register (BANK=1)
1 10-month counteDrataSheet4U.com(BANK=0)
MO8
MO4
D20
MO2
D10
MO1 DataShee
CLEN*7
MO10
0 1-year counter
(BANK=0)
Y8
Y4
Y2
Y1
1 10-year counter
0 Control register 1
1 Control register 2
(BANK=0)
(BANK=0, 1)
(BANK=0, 1)
Y80
12/24
Y40 Y20 Y10
WTE*N6/XST*P4 ADJ/BSY *3
— BANK *5 TEST *6
*1) All the listed data can be read and written.
*2) The “—” mark indicates data which can be read only and set to “0” when read.
*3) The ADJ/BSY bit of the control register is set to ADJ for write operation and BSY for read operation.
*4) The WTEN/XSTP bit of the control register is set to WTEN for write operation and XSTP for read operation.
*5) The clock/calendar counter and the 32kHz clock pulse control register can be selected when the BANK=0 and BANK=1 respectively. To designate
the BANK is unnecessary for scratch register and control register 1/2.
*6) The WTEN bit and TEST bit are set to “1” when CE is “L”.
*7) The CLEN bit is set to 0, when initial power-on or XSTP is set to 1.
*8) Data may be written and read into/from the Scratch register, which actually is not used.
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