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PDF LTC1235CS Data sheet ( Hoja de datos )
| Número de pieza | LTC1235CS | |
| Descripción | Microprocessor Supervisory Circuit | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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FEATURES
s Guaranteed Reset Assertion at VCC = 1V
s 1.5mA Maximum Supply Current
s Fast (35ns Max.) Onboard Gating of RAM Chip
Enable Signals
s Conditional Battery Backup Extends Battery Life
s 4.65V Precision Voltage Monitor
s Power OK/Reset Time Delay: 200ms
s External Reset Control
s Minimum External Component Count
s 1µA Maximum Standby Current
s Voltage Monitor for Power Fail or Low Battery
Warning
s Thermal Limiting
s Performance Specified Over Temperature
s All the LTC695 Features Plus Conditional Battery
Backup and External Reset Control
APPLICATI S
s Critical µP Power Monitoring
s Intelligent Instruments
s Battery-Powered Computers and Controllers
s Automotive Systems
LTC1235
Microprocessor
Supervisory Circuit
DESCRIPTIO
The LTC1235 provides complete power supply monitoring
and battery control functions for microprocessor reset,
battery backup, RAM write protection, power failure warn-
ing and watchdog timing. The LTC1235 has all the LTC695
features plus conditional battery backup and external reset
control. When an out-of-tolerance power supply condition
occurs, the reset outputs are forced to active states and the
Chip Enable output write-protects external memory. The
RESET output is guaranteed to remain logic low with VCC as
low as 1V. External reset control is provided by a debounced
push-button reset input.
The LTC1235 powers the active CMOS RAMs with a charge
pumped NMOS power switch to achieve low dropout and
low supply current. When primary power is lost, auxiliary
power, connected to the battery input pin, provides backup
power to the RAMs. The LTC1235 can be programmed by
a µP signal to either back up the RAMs or not. This extends
the battery life in situations where RAM data need not
always be saved when power goes down.
For an early warning of impending power failure, the
LTC1235 provides an internal comparator with a user-
defined threshold. An internal watchdog timer is also avail-
able, which forces the reset pins to active states when the
watchdog input is not toggled prior to the time-out period.
TYPICAL APPLICATI
VIN ≥ 7.5V
+
10µF
LT1086-5
VIN VOUT
ADJ
+5V
+
100µF
51k
10k
VCC VOUT
0.1µF
LTC1235
VBATT BACKUP
+3V RESET
PFI
PB RST
PFO
WDI
POWER TO µP
0.1µF CMOS RAM POWER
I/O LINE
µP RESET
µP NMI
I/O LINE
µP
SYSTEM
LTC1235 TA1
THE LTC1235 EXTENDS BATTERY LIFE BY PROVIDING BATTERY POWER ONLY WHEN REQUIRED TO BACK UP RAM DATA.
IT SAVES THE BATTERY WHEN NO DATA BACKUP IS NEEDED. THE µP REQUESTS BACKUP WITH THE BACKUP PIN.
Battery Life vs
Backup Duty Cycle
10
9
LTC1235
8
7
6
5 LTC695
4
(WITHOUT
CONDITIONAL
3 BATTERY
BACKUP)
2
1
0
0 20 40 60 80 100
BACKUP DUTY CYCLE (%)
LTC1235 TA02
1
1 page  
LTC1235
TYPICAL PERFOR A CE CHARACTERISTICS
VOUT vs IOUT
5.00
4.95
4.90
SLOPE = 5Ω
4.85
4.80
VCC = 5V
VBATT = 2.8V
TA = 25°C
VOUT vs IOUT
2.80
2.78
SLOPE = 125Ω
2.76
VCC = 0V
VBATT = 2.8V
TA = 25°C
BACKUP MODE
SELECTED
2.74
4.75
0
10 20 30 40
LOAD CURRENT (mA)
50
LTC1235 G01
RESET Output Voltage vs Supply
Voltage
5
TA = 25°C
EXTERNAL PULLUP = 10µA
4 VBATT = 0V
3
2
1
0
01 2 345
SUPPLY VOLTAGE (V)
LTC1235 G04
Power Fail Comparator
Response Time
6
5
VCC = 5V
TA = 25°C
4
3 VPFI +
2
1.3V
PFO
–
30pF
1
0
2.72
0
100 200 300 400
LOAD CURRENT (µA)
500
LTC1235 G02
Reset Active Time vs
Temperature
232
VCC = 5V
224
216
208
200
192
184
–50 –25
0 25 50 75
TEMPERATURE (°C)
100 125
LTC1235 G05
Power Fail Comparator
Response Time
6
5
VCC = 5V
TA = 25°C
4
3
2 VPFI +
1
1.3V
PFO
–
0
30pF
1.305V
1.285V
VPFI = 20mV STEP
01 2 34 567 8
TIME (µs)
LTC1235 G07
1.315V
1.295V
VPFI = 20mV STEP
0 20 40 60 80 100 120 140 160 180
TIME (µs)
LTC1235 G08
Power Failure Input Threshold
vs Temperature
1.308
1.306
VCC = 5V
1.304
1.302
1.300
1.298
1.296
1.294
–50 –25
0 25 50 75
TEMPERATURE (˚C)
100 125
LTC1235 G03
Reset Voltage Threshold
vs Temperature
4.66
4.65
4.64
4.63
4.62
4.61
4.60
–50 –25
0 25 50 75
TEMPERATURE (°C)
100 125
LTC1235 G06
Power Fail Comparator Response
Time with Pullup Resistor
6
5
VCC = 5V
TA = 25°C
4
3
2
1 +5V
VPFI +
10k
0
1.3V
PFO
–
30pF
1.315V
1.295V
VPFI = 20mV STEP
0 2 4 6 8 10 12 14 16 18
TIME (µs)
LTC1235 G09
5
5 Page 
LTC1235
APPLICATI S I FOR ATIO
Table 1 shows the state of each pin during battery backup.
If the backup battery is not used, connect VBATT to GND
and VOUT to VCC.
Table 1. Input and Output Status in Battery Backup Mode
SIGNAL STATUS
VCC C2 monitors VCC for active switchover.
BACKUP BACKUP is ignored.
VOUT
VBATT
BATT ON
PFI
VOUT is connected to VBATT through an internal PMOS switch.
The supply current is 1µA maximum.
Logic high. The open circuit output voltage is equal to VOUT.
Power Failure Input is ignored.
PFO Logic low
PB RST PB RST is ignored.
RESET Logic low
RESET Logic high. The open circuit output voltage is equal to VOUT.
LOW LINE Logic low
WDI Watchdog Input is ignored.
WDO
CE IN
Logic high. The open circuit output voltage is equal to VOUT.
Chip Enable Input is ignored.
CE OUT Logic high. The open circuit output voltage is equal to VOUT.
Memory Protection
The LTC1235 includes memory protection circuitry which
ensures the integrity of the data in memory by preventing
write operations when VCC is at invalid level. Two pins, CE
IN and CE OUT, control the Chip Enable or Write inputs of
CMOS RAM. When VCC is +5V, CE OUT follows CE IN with
a typical propagation delay of 20ns. When VCC falls below
the reset voltage threshold or VBATT, CE OUT is forced
high, independent of CE IN. CE OUT is an alternative signal
to drive the CE, CS, or Write input of battery-backed up
CMOS RAM. CE OUT can also be used to drive the Store
or Write input of an EEPROM, EAROM or NOVRAM to
achieve similar protection. Figure 6 shows the timing
diagram of CE IN and CE OUT.
CE IN can be derived from the microprocessor’s address
decoder output. Figure 7 shows a typical nonvolatile
CMOS RAM application.
+5V
0.1µF
+3V
VCC VOUT
LTC1235
CE OUT
VBATT CE IN
BACKUP
GND RESET
+
10µF
0.1µF
VCC
62512
RAM
CSGND
20ns PROPAGATION DELAY
FROM DECODER
TO µP
LTC1235 F06
Figure 7. A Typical Nonvolatile CMOS RAM Application
BACKUP = VCC
VCC
V2
V1 V1 = RESET VOLTAGE THRESHOLD
V2 = RESET VOLTAGE THRESHOLD +
RESET THRESHOLD HYSTERESIS
CE IN
CE OUT
VOUT = VBATT
Figure 6. Timing Diagram for CE IN and CE OUT
VOUT = VBATT
LTC1235 F06
11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet LTC1235CS.PDF ] | |
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