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PDF LTC1198 Data sheet ( Hoja de datos )
| Número de pieza | LTC1198 | |
| Descripción | 8-Bit/ SO-8/ 1MSPS ADCs with Auto-Shutdown Options | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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LTC1196/LTC1198
8-Bit, SO-8, 1MSPS ADCs with
Auto-Shutdown Options
FEATURES
s High Sampling Rates: 1MHz (LTC1196)
750kHz (LTC1198)
s Low Cost
s SO-8 Plastic Package
s Single Supply 3V and 5V Specifications
s Low Power: 10mW at 3V Supply
50mW at 5V Supply
s Auto-Shutdown: 1nA Typical (LTC1198)
s ±1/2LSB Total Unadjusted Error over Temperature
s 3-Wire Serial I/O
s 1V to 5V Input Span Range (LTC1196)
s Converts 1MHz Inputs to 7 Effective Bits
s Differential Inputs (LTC1196)
s 2-Channel MUX (LTC1198)
APPLICATI S
s High Speed Data Acquisition
s Disk Drives
s Portable or Compact Instrumentation
s Low Power or Battery-Operated Systems
DESCRIPTIO
The LTC1196/LTC1198 are 600ns, 8-bit A/D converters
with sampling rates up to 1MHz. They are offered in 8-pin
SO packages and operate on 3V to 6V supplies. Power
dissipation is only 10mW with a 3V supply or 50mW with
a 5V supply. The LTC1198 automatically powers down to
a typical supply current of 1nA whenever it is not perform-
ing conversions. These 8-bit switched-capacitor succes-
sive approximation ADCs include sample-and-holds. The
LTC1196 has a differential analog input; the LTC1198
offers a software selectable 2-channel MUX.
The 3-wire serial I/O, SO-8 packages, 3V operation and
extremely high sample rate-to-power ratio make these
ADCs an ideal choice for compact, high speed systems.
These ADCs can be used in ratiometric applications or with
external references. The high impedance analog inputs
and the ability to operate with reduced spans below 1V full
scale (LTC1196) allow direct connection to signal sources
in many applications, eliminating the need for gain stages.
The A grade devices are specified with total unadjusted
error of ±1/2LSB maximum over temperature.
TYPICAL APPLICATI
Single 5V Supply, 1MSPS, 8-Bit Sampling ADC
1µF 5V
ANALOG INPUT
0V TO 5V RANGE
1 CS
8
VCC
27
+IN LTC1196 CLK
3 (SO-8) 6
–IN DOUT
4 GND
5
VREF
SERIAL DATA LINK TO
ASIC, PLD, MPU, DSP,
OR SHIFT REGISTERS
1196/98 TA01
Effective Bits and S/(N + D) vs Input Frequency
8
7
VREF = VCC = 2.7V
fSMPL = 383kHz (LTC1196)
fSMPL = 287kHz (LTC1198)
6 VREF = VCC = 5V
5
fSMPL = 1MHz (LTC1196)
fSMPL = 750kHz (LTC1198)
4
50
44
3
2
1
TA = 25°C
0
1k 10k
100k
INPUT FREQUENCY (Hz)
1M
1196/98 G24
1
1 page  
LTC1196/LTC1198
RECO E DED OPERATI G CO DITIO S
VCC = 2.7V Operation
SYMBOL PARAMETER
CONDITIONS
LTC1196-1
LTC1198-1
MIN TYP MAX
LTC1196-2
LTC1198-2
MIN TYP MAX
thDI
tsuDI
tWHCLK
tWLCLK
tWHCS
tWLCS
Hold Time DIN After CLK↑
Setup Time DIN Stable Before CLK↑
CLK High Time
CLK Low Time
CS High Time Between Data Transfer Cycles
CS Low Time During Data Transfer
LTC1198
LTC1198
fCLK = fCLK(MAX)
fCLK = fCLK(MAX)
LTC1196
LTC1198
40
40
40%
40%
50
11
15
78
78
40%
40%
96
11
15
U UW
CO VERTER A D ULTIPLEXER CHARACTERISTICS
VCC = 2.7V, VREF = 2.5V, fCLK = fCLK(MAX) as defined in Recommended Operating Conditions, unless otherwise noted.
PARAMETER
CONDITIONS
LTC1196-XA
LTC1198-XA
MIN TYP MAX
LTC1196-XB
LTC1198-XB
MIN TYP MAX
No Missing Codes Resolution
q8
8
Offset Error
q ±1/2
±1
Linearity Error
(Note 3)
q ±1/2
±1
Full-Scale Error
q ±1/2
±1
Total Unadjusted Error (Note 4)
Analog and REF Input Range
Analog Input Leakage Current
LTC1196, VREF = 2.500V
LTC1198, VCC = 2.700V
LTC1196
(Note 5)
q
q
±1/2
– 0.05V to VCC + 0.05V
±1
±1
±1
UNITS
ns
ns
1/fCLK
1/fCLK
ns
CLK
CLK
UNITS
Bits
LSB
LSB
LSB
LSB
V
µA
DIGITAL A D DC ELECTRICAL CHARACTERISTICS
VCC = 2.7V, VREF = 2.5V, unless otherwise noted.
SYMBOL PARAMETER
CONDITIONS
VIH
VIL
IIH
IIL
VOH
VOL
IOZ
ISOURCE
ISINK
IREF
ICC
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
High Level Output Voltage
Low Level Output Voltage
Hi-Z Output Leakage
Output Source Current
Output Sink Current
Reference Current, LTC1196
Supply Current
VCC = 3.6V
VCC = 2.7V
VIN = VCC
VIN = 0V
VCC = 2.7V, IO = 10µA
VCC = 2.7V, IO = 360µA
VCC = 2.7V, IO = 400µA
CS = High
VOUT = 0V
VOUT = VCC
CS = VCC
fSMPL = fSMPL(MAX)
CS = VCC = 3.3V, LTC1198 (Shutdown)
CS = VCC = 3.3V, LTC1196
fSMPL = fSMPL(MAX), LTC1196/LTC1198
MIN TYP MAX UNITS
q 1.9
V
q 0.45 V
q 2.5 µA
q – 2.5 µA
q 2.3 2.60
q 2.1 2.45
V
V
q 0.3 V
q ±3 µA
– 10 mA
15 mA
q
0.001 3.0
µA
q
0.25 0.5
mA
q
0.001 3.0
µA
q
1.5 4.5
mA
q
2.0 6.0
mA
5
5 Page 
LTC1196/LTC1198
PI FU CTIO S
LTC1196
CS (Pin 1): Chip Select Input. A logic low on this input
enables the LTC1196. A logic high on this input disables
the LTC1196.
IN+ (Pin 2): Analog Input. This input must be free of noise
with respect to GND.
IN– (Pin 3): Analog Input. This input must be free of noise
with respect to GND.
GND (Pin 4): Analog Ground. GND should be tied directly
to an analog ground plane.
VREF (Pin 5): Reference Input. The reference input defines
the span of the A/D converter and must be kept free of
noise with respect to GND.
DOUT (Pin 6): Digital Data Output. The A/D conversion
result is shifted out of this output.
CLK (Pin 7): Shift Clock. This clock synchronizes the serial
data transfer.
VCC (Pin 8): Power Supply Voltage. This pin provides
power to the A/D converter. It must be kept free of noise
and ripple by bypassing directly to the analog ground
plane.
LTC1198
CS/SHUTDOWN (Pin 1): Chip Select Input. A logic low on
this input enables the LTC1198. A logic high on this input
disables the LTC1198 and DISCONNECTS THE POWER TO
THE LTC1198.
CHO (Pin 2): Analog Input. This input must be free of noise
with respect to GND.
CH1 (Pin 3): Analog Input. This input must be free of noise
with respect to GND.
GND (Pin 4): Analog Ground. GND should be tied directly
to an analog ground plane.
DIN (Pin 5): Digital Data Input. The multiplexer address is
shifted into this input.
DOUT (Pin 6): Digital Data Output. The A/D conversion
result is shifted out of this output.
CLK (Pin 7): Shift Clock. This clock synchronizes the serial
data transfer.
VCC(VREF)(Pin 8): Power Supply and Reference Voltage.
This pin provides power and defines the span of the A/D
converter. It must be kept free of noise and ripple by
bypassing directly to the analog ground plane.
BLOCK DIAGRA
IN+ (CH0)
IN– (CH1)
VCC (VCC/VREF)
CS
(CS/SHUTDOWN) CLK
BIAS AND
SHUTDOWN CIRCUIT
SERIAL PORT
CSMPL
–
+ HIGH SPEED
COMPARATOR
CAPACITIVE DAC
SAR
DOUT
PIN NAMES IN PARENTHESES
REFER TO THE LTC1198
GND
VREF (DIN)
1196/98 BD
11
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet LTC1198.PDF ] | |
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