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PDF LTC1064-7CN Data sheet ( Hoja de datos )
| Número de pieza | LTC1064-7CN | |
| Descripción | Linear Phase/ 8th Order Lowpass Filter | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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LTC1064-7
Linear Phase, 8th Order
Lowpass Filter
FEATURES
s Steeper Roll-Off Than 8th Order Bessel Filters
s fCUTOFF up to 100kHz
s Phase Equalized Filter in 14-Pin Package
s Phase and Group Delay Response Fully Tested
s Transient Response Exhibits 5% Overshoot and
No Ringing
s Wide Dynamic Range
s 72dB THD or Better Throughout a 50kHz Passband
s No External Components Needed
APPLICATI S
s Data Communication Filters
s Time Delay Networks
s Phase-Matched Filters
DESCRIPTIO
The LTC1064-7 is a clock-tunable monolithic 8th order
lowpass filter with linear passband phase and flat group
delay. The amplitude response approximates a maximally
flat passband whilte it exhibits steeper roll-off than an
equivalent 8th order Bessel filter. For instance, at twice the
cutoff frequency the filter attains 34dB attenuation (vs
12dB for Bessel), while at three times the cutoff frequency
the filter attains 68dB attenuation (vs 30dB for Bessel).
The cutoff frequency of the LTC1064-7 is tuned via an
external TTL or CMOS clock.
The LTC1064-7 features wide dynamic range. With single
5V supply, the S/N + THD is 76dB. Optimum 92dB S/N is
obtained with ±7.5V supplies.
The clock-to-cutoff frequency ratio of the LTC1064-7 can
be set to 50:1 (pin 10 to V+) or 100:1 (pin 10 to V –).
When the filter operates at clock-to-cutoff frequency ratio
of 50:1, the input is double-sampled to lower the risk of
aliasing.
The LTC1064-7 is pin-compatible with the LTC1064-X
series, LTC1164-7 and LTC1264-7.
TYPICAL APPLICATI
80kHz Linear Phase Lowpass Filter
1 14
VIN 2
3
13
12 –7.5V
7.5V
4 LTC1064-7 11
CLK = 4MHz
5 10 7.5V
6 9 VOUT
78
1064-7 TA01
NOTE: THE POWER SUPPLIES SHOULD BE BYPASSED BY A
0.1µF CAPACITOR CLOSE TO THE PACKAGE AND ANY PRINTED
CIRCUIT BOARD ASSEMBLY SHOULD MAINTAIN A DISTANCE
OF AT LEAST 0.2 INCHES BETWEEN ANY OUTPUT OR INPUT
PIN AND THE fCLK LINE.
Eye Diagram
VS = ±7.5V
fCLK = 4MHz
RATIO = 50:1
1µs/DIV
1064-7 TA02
1
1 page  
TYPICAL PERFOR A CE CHARACTERISTICS
LTC1064-7
Passband Gain vs Frequency
and fCLK
5
4
VS = ±7.5V
TA = 25°C
3 (fCLK/fC) = 50:1
2
A. fCLK = 1MHz
B. fCLK = 2MHz
C. fCLK = 3MHz
D. fCLK = 4MHz
E. fCLK = 5MHz
1
0
–1
–2 D
A BC E
–3
–4
–5
10
10 100
FREQUENCY (kHz)
1000
1064-7 G08
Passband Gain vs Frequency
and fCLK
5
4
VS = SINGLE 5V
TA = 25°C
3 (fCLK/fC) = 50:1
2
A. fCLK = 0.5MHz
B. fCLK = 1.0MHz
C. fCLK = 1.5MHz
D. fCLK = 2.0MHz
1
0
–1
–2
A B CD
–3
–4
–5
1
10
FREQUENCY (kHz)
100
1064-7 G11
Delay vs Frequency and fCLK
250
A
200
VS = ±5V
TA = 25°C
(fCLK/fC) = 100:1
150
100 B
A. fCLK = 0.5MHz
B. fCLK = 1.5MHz
C. fCLK = 2.5MHz
D. fCLK = 3.5MHz
50 C
D
0
1
6
11 16 21 26
FREQUENCY (kHz)
31 36
1064-7 G14
Passband Gain vs Frequency and
fCLK at TA = 85°C
5
4
VS = ±7.5V
(fCLK/fC) = 50:1
3
2
A. fCLK = 1MHz
B. fCLK = 2MHz
C. fCLK = 3MHz
D. fCLK = 4MHz
E. fCLK = 5MHz
1
0
–1
D
–2
A BC E
–3
–4
–5
1 10 100 1000
FREQUENCY (kHz)
1064-7 G09
Passband Gain vs Frequency and
fCLK at TA = 85°C
5
4
VS = SINGLE 5V
(fCLK/fC) = 50:1
3
2
A. fCLK = 0.5MHz
B. fCLK = 1.0MHz
C. fCLK = 1.5MHz
D. fCLK = 2.0MHz
1
0
–1
–2
A B CD
–3
–4
–5
1
10
FREQUENCY (kHz)
100
1064-7 G12
THD + Noise vs Frequency
– 40
– 45
VS = ±7.5V
VIN = 2VRMS
–50 fCLK = 1MHz
– 55
(fCLK/fC) = 50:1
(100k RESISTOR
–60 PIN 9 TO V–)
– 65
– 70
– 75
– 80
– 85
– 90
1
10
FREQUENCY (kHz)
20
1064-7 G15
Passband Gain vs Frequency and
fCLK at TA = 85°C
5
4
VS = ±5V
(fCLK/fC) = 50:1
3
2
A. fCLK = 0.5MHz
B. fCLK = 1.5MHz
C. fCLK = 2.5MHz
D. fCLK = 3.5MHz
1
0
–1
–2
–3 A B C D
–4
–5
1 10 100
FREQUENCY (kHz)
1064-7 G10
Delay vs Frequency and fCLK
125
A
100
VS = ±5V
TA = 25°C
(fCLK/fC) = 50:1
75
50 B
A. fCLK = 0.5MHz
B. fCLK = 1.5MHz
C. fCLK = 2.5MHz
D. fCLK = 3.5MHz
25 C
D
0
2 12
22 32 42 52
FREQUENCY (kHz)
62 72
1064-7 G13
THD + Noise vs Frequency
– 40
– 45
VS = ±7.5V
VIN = 1VRMS
–50 fCLK = 2.5MHz
– 55
(fCLK/fC) = 50:1
(100k RESISTOR
–60 PIN 9 TO V–)
– 65
– 70
– 75
– 80
– 85
– 90
1
10
FREQUENCY (kHz)
50
1064-7 G16
5
5 Page 
LTC1064-7
APPLICATI S I FOR ATIO
Speed Limitations
To avoid op amp slew rate limiting at maximum clock
frequencies, the signal amplitude should be kept below a
specified level as shown in Table 9.
Transient Response
Table 9. Maximum VIN vs VS and Clock
POWER SUPPLY
±7.5V
±5V
Single 5V
MAXIMUM fCLK
5.0MHz
4.5MHz
4.0MHz
≥ 3.5MHz
3.5MHz
≥ 3.0MHz
2.0MHz
MAXIMUM VIN
1.8VRMS (fIN > 80kHz)
2.3VRMS (fIN > 80kHz)
2.7VRMS (fIN > 80kHz)
1.4VRMS (fIN > 500kHz)
1.6VRMS (fIN > 80kHz)
0.7VRMS (fIN > 400kHz)
0.5VRMS (fIN > 250kHz)
Table 10. Transient Response of LTC Lowpass Filters
LOWPASS FILTER
DELAY
TIME*
(SEC)
RISE SETTLING
TIME** TIME***
(SEC) (SEC)
LTC1064-3 Bessel
0.50/fC 0.34/fC 0.80/fC
LTC1164-5 Bessel
0.43/fC 0.34/fC 0.85/fC
LTC1164-6 Bessel
0.43/fC 0.34/fC 1.15/fC
LTC1264-7 Linear Phase 1.15/fC 0.36/fC 2.05/fC
LTC1164-7 Linear Phase 1.20/fC 0.39/fC 2.2/fC
LTC1064-7 Linear Phase 1.20/fC 0.39/fC 2.2/fC
LTC1164-5 Butterworth
0.80/fC 0.48/fC 2.4/fC
LTC1164-6 Elliptic
0.85/fC 0.54/fC 4.3/fC
LTC1064-4 Elliptic
0.90/fC 0.54/fC 4.5/fC
LTC1064-1 Elliptic
0.85/fC 0.54/fC 6.5/fC
* To 50% ±5%, ** 10% to 90% ±5%, *** To 1% ±0.5%
OVER-
SHOOT
(%)
0.5
0
1
5
5
5
11
18
20
20
Table 11. Aliasing (fCLK = 100kHz)
INPUT FREQUENCY
(VIN = 1VRMS,
fIN = fCLK ± fOUT)
(kHz)
OUTPUT LEVEL
(Relative to Input,
0dB = 1VRMS)
(dB)
50:1, fCUTOFF = 2kHz
190 (or 210)
195 (or 205)
196 (or 204)
197 (or 203)
198 (or 202)
199.5 (or 200.5)
–76.1
– 51.9
– 36.3
– 18.4
– 3.0
– 0.2
100:1, fCUTOFF = 1kHz
97 (or 103)
97.5 (or 102.5)
98 (or 102)
98.5 (or 101.5)
99 (or 101)
–74.2
– 53.2
– 36.9
– 19.6
– 5.2
99.5 (or 100.5)
– 0.7
OUTPUT FREQUENCY
(Aliased Frequency
fOUT = ABS [fCLK ± fIN])
(kHz)
10.0
5.0
4.0
3.0
2.0
0.5
3.0
2.5
2.0
1.5
1.0
0.5
50µs/DIV
VS = ±7.5V, fIN = 2kHz ± 3V
fCLK = 1MHz, RATIO = 50:1
Figure 5.
INPUT
90%
ts
1064-7 F05
OUTPUT
50% td
10% tr
RISE
TIME
(tr)
=
0.39
fCUTOFF
±
5%
SETTLING
(TO 1% of
TIME (ts)
OUTPUT)
=
2.2
fCUTOFF
±5%
DELAY TIME (td) = GROUP
(TO 50% OF OUTPUT)
DELAY
≈
1.2
fCUTOFF
1064-7 F06
Figure 6.
Aliasing
Aliasing is an inherent phenomenon of sampled data
systems and it occurs when input frequencies close to the
sampling frequency are applied. For the LTC1064-7 case
at 100:1, an input signal whose frequency is in the range
of fCLK ±3%, will be aliased back into the filter’s passband.
If, for instance, an LTC1064-7 operating with a 100kHz
clock and 1kHz cutoff frequency receives a 98kHz, 10mV
input signal, a 2kHz, 143µVRMS alias signal will appear at
its output. When the LTC1064-7 operates with a clock-to-
cutoff frequency of 50:1, aliasing occurs at twice the clock
frequency. Table 11 shows details.
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet LTC1064-7CN.PDF ] | |
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