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PDF NDS352P Data sheet ( Hoja de datos )
| Número de pieza | NDS352P | |
| Descripción | P-Channel Logic Level Enhancement Mode Field Effect Transistor | |
| Fabricantes | Fairchild | |
| Logotipo |  |
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March 1996
NDS352P
P-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
Features
These P-Channel logic level enhancement mode power
field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This
very high density process is especially tailored to
minimize on-state resistance. These devices are
particularly suited for low voltage applications such as
notebook computer power management, portable
electronics, and other battery powered circuits where fast
high-side switching, and low in-line power loss are
needed in a very small outline surface mount package.
-0.85A, -20V. RDS(ON) = 0.5Ω @ VGS = -4.5V.
Proprietary package design using copper lead frame for
superior thermal and electrical capabilities.
High density cell design for extremely low RDS(ON).
Exceptional on-resistance and maximum DC current
capability.
Compact industry standard SOT-23 surface mount
package.
____________________________________________________________________________________________
D
GS
Absolute Maximum Ratings
Symbol Parameter
TA = 25°C unless otherwise noted
VDSS
Drain-Source Voltage
VGSS
Gate-Source Voltage - Continuous
ID Maximum Drain Current - Continuous
- Pulsed
PD Maximum Power Dissipation
(Note 1a)
(Note 1a)
(Note 1b)
TJ,TSTG Operating and Storage Temperature Range
THERMAL CHARACTERISTICS
RθJA
RθJC
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Case
(Note 1a)
(Note 1)
NDS352P
-20
±12
±0.85
±10
0.5
0.46
-55 to 150
250
75
© 1997 Fairchild Semiconductor Corporation
Units
V
V
A
W
°C
°C/W
°C/W
NDS352P Rev. F1
1 page  
Typical Electrical Characteristics (continued)
1.15
1.1
ID = -250µA
1.05
1
0.95
0.9
-50
-25
0 25 50 75 100 125 150
TJ , JUNCTION TEMPERATURE (°C)
Figure 7. Breakdown Voltage Variation with
Temperature
5
VGS = 0V
1
0.5
TJ = 125°C
25°C
0.1 -55°C
0.01
0 0.4 0.8 1.2 1.6 2 2.4
-VSD , BODY DIODE FORWARD VOLTAGE (V)
Figure 8. Body Diode Forward Voltage Variation with
Source Current and Temperature
500
300
200
Ciss
100
Coss
50
30
20
0.1
f = 1 MHz
VGS = 0 V
Crss
0.2
0.5 1
2
5 10
-VDS , DRAIN TO SOURCE VOLTAGE (V)
20
Figure 9. Capacitance Characteristics
-10
-8
-6
-4
-2
0
0
I = -850m A
D
V DS = -5V
-10
123
Q g , GATE CHARGE (nC)
4
Figure 10. Gate Charge Characteristics
VIN
VGS
RGEN
G
VDD
RL
D
V OUT
DUT
S
Figure 11. Switching Test Circuit
t d(on)
ton
tr
90%
td(off)
toff
tf
90%
VO U T
VIN
10%
10%
50%
10%
90%
50%
PULSE WIDTH
INVERTED
Figure 12. Switching Waveforms
NDS352P Rev. F1
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet NDS352P.PDF ] | |
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