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PDF STV5348 Data sheet ( Hoja de datos )
| Número de pieza | STV5348 | |
| Descripción | MONOCHIP TELETEXT AND VPS DECODER | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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STV5348
MONOCHIP TELETEXT AND VPS DECODER
WITH 8 INTEGRATED PAGES
FEATURES SUMMARY
■ COMPLETE TELETEXT AND VPS DECODER
INCLUDING AN 8 PAGE MEMORY ON A
SINGLE CHIP
Figure 1. Package
■ UPWARD SOFTWARE COMPATIBLE WITH
PREVIOUS ST’s MULTICHIP SOLUTIONS
(SAA5231, SDA5243, STV5345)
■ PERFORM PDC SYSTEM A (VPS) AND PDC
SYSTEM B (8/30/2) DATA STORAGE
)SEPARATELY
t(s■ DEDICATED "ERROR FREE" OUTPUT FOR
cVALID PDC DATA
du■ INDICATION OF LINE 23 FOR EXTERNAL
roUSE
P■ SINGLE +5V SUPPLY VOLTAGE
te■ SINGLE 13.875MHz CRYSTAL
le■ REDUCED SET OF EXTERNAL
oCOMPONENTS, NO EXTERNAL
sADJUSTMENT
Ob■ OPTIMIZED NUMBER OF DIGITAL SIGNALS
-REDUCING EMC RADIATION
)■ HIGH DENSITY CMOS TECHNOLOGY
t(s■ DIGITAL DATA SLICER AND DISPLAY
cCLOCK PHASE LOCK LOOP
du■ 28 PIN DIP & SO PACKAGE
ProDESCRIPTION
teThe STV5348 decoder is a computer-controlled
leteletext device including an 8 page internal mem-
ory. Data slicing and capturing extracts the teletext
oinformation embedded in the composite video sig-
bsnal. Control is accomplished via a two wire serial
OI2C bus ®. Chip address is 22h. Internal ROM pro-
PDIP28 (Plastic Package)
SO28 (Plastic Package)
Figure 2. Pin Connections
CVBS
MA/SL
VDDA
POL
STTV/LFB
FFB
VSSD
R
G
1
2
3
4
5
6
7
8
9
28 CBLK
27 TEST
26 VSSA
25 VSSO
24 XTI
23 XTO
22 VDDD
21 VCR/TV
20 RESERVED
vides a character set suitable to display text using
up to seven national languages. Hardware and
B 10
19 DV
software features allow selectable master/slave
RGB REF
11
18 L23
synchronization configurations. The STV5348
also supports facilities for reception and display of
BLAN
12
17 SDA
current level protocol data.
COR
13
16 SCL
ODD/EVEN
14
15 Y
May 2004
REV. 2
1/30
1 page  
STV5348
Table 5. Outputs
Symbol
Parameter
Min.
Typ.
Max.
Unit
RGB
VOL Output Low Voltage (IOL = 2mA)
0.4 V
VOH Output High Voltage (IOH = –2mA, RGB REF = VDD/2) RGB REF – 0.5
RGB REF
V
CL Load Capacitance
50 pF
tR, tF Rise and Fall Time (10 to 90%)
20 ns
BLAN
VOL Output Low Voltage (IOL = 2mA)
0 0.4 V
VOH Output High Voltage (IOH = –0.2mA)
VDD – 0.5
V
CL Load Capacitance
50 pF
tR, tF Rise and Fall Time (10 to 90%)
20 ns
ODD/EVEN, STTV, L23, DV
)VOL Output Low Voltage (IOL = 2mA)
t(sVOH Output High Voltage (IOH = –0.2mA)
ucCL Load Capacitance
dtR, tF Rise and Fall Time (10 to 90%)
roCOR AND COR AND Y (with Pull up to VDDD)
te PVOL Output Low Voltage (IOL = 2mA)
leCL Load Capacitance
otF Fall Time (RL = 1.2kΩ, VDDD – 0.5V to 1.5V)
bsIOLL Output Leakage Current
OSDA
) -VOL Output Low Voltage (IOL = 3mA)
t(stF Fall Time (3.0 to 1.0V)
ucCL Load Capacitance
rodTable 6. Crystal Oscillator
PSymbol
Parameter
tefXTAL Crystal Frequency
leRBIAS Internal Bias Resistance
ObsoCI Input Capacitance
0
VDD – 0.8
0
–10
0
0.5 V
VDD
V
50 pF
20 ns
0.5 V
25 V
50 ns
+10 µs
0.5 V
200 ns
400 pF
Min.
0.4
Typ.
13.875
1
Max.
3
7
Unit
MHz
MΩ
pF
5/30
5 Page 
STV5348
Table 9. Row 25 Received Page Control Data Format
D0
D1
D2
D3
D4
D5
D6
D7
COLUMN
PU0
PU1
PU2
PU3
HAM
0
0
0
0
PT0
PT1
PT2
PT3
HAM
0
0
0
1
MU0
MU1
MU2
MU3
HAM
0
0
0
2
MT0
MT1
MT2
C4
HAM
0
0
0
3
HU0
HU1
HU2
HU3
HAM
0
0
0
4
HT0
HT1
C5
C6
HAM
0
0
0
5
C7
C8
C9
C10
HAM
0
0
0
6
C11
C12
C13
C14
HAM
0
0
0
7
MAG0
MAG1
MAG2
0
FOUND
0
0
0
8
0
0
0
0
0
PBLF
0
0
9
Page number : - MAG = magazine, PU = page units, PT = page tens.
Page sub-code : - MU = minutes units, MT = minutes tens, HU = hours units, HT = hours tens.
PBLF = page being looked for, FOUND = low for page found, HAM = hamming error in byte, C4-14 = control bits.
)VPS DATA (see Table 10)
t(sVPS data are stored in row 25 chapter 5 as shown
cin Table 10 when VPS enable bit (D4 of R8 regis-
uter) is set. VPS data bits are decoded and stored
din a received area with biphase error bit.
ro8/30/2 data are stored as received (without ham-
Pming decoding) in Row 23 chapter 5 according to
Table 10.
te8/30 packet and VPS data decoding is the respon-
lesibility of the control software. The decoder simply
ostores transmitted data.
sI2C Bus Register Map (see Table 11)
bRegisters R0 to R10 are write only whilst R11A is
Oa read/write and R11B is read only.
The automatic succession on a byte by byte basis
is indicated by the arrows in Table 10.
In the normal operating mode TB should be set to
logic level 0.
After power-up the contents of the registers are as
follows: all bits in registers R0 to R11A are cleared
to zero with the exception of bits D0 and D1 in reg-
isters R5 and R6 which are set to logical one.
After power-up all the memory bytes are preset to
hexadecimal value 20H (space) with the exception
of the byte corresponding to row 0 of column 7 of
chapter 0 which is set to the value corresponding
to "alpha white" hexadecimal value 07H.
t(s) -Table 10. PDC Data Storage
cColumn
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
u8/30/2 (Row 23) D
Initial Page
b13 b14 b15 b16 b17 b18 b19 b20 b21 b22 b23 b24 b25
rodVPS (Row 25)
Received Page Information
B11 B12 B13 B14 B15
PColumn
20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
te8/30/2 (Row 23)
Status Display
ObsoleVPS (Row 25) B4
B5
11/30
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet STV5348.PDF ] | |
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