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PDF NT68P61A Data sheet ( Hoja de datos )
| Número de pieza | NT68P61A | |
| Descripción | 8-Bit Microcontroller for Monitor (24K OTP ROM Type) | |
| Fabricantes | ETC | |
| Logotipo |  |
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NT68P61A
8-Bit Microcontroller for Monitor (24K OTP ROM Type)
Features
T 40 pin DIP & 42 pin SDIP package
T Operating Voltage Range: 4.5V to 5.5V
T CMOS technology for low power consumption
T Crystal oscillator or ceramic resonator* available
T 6502 8-bit CMOS CPU core
T 8MHz operation of frequency
T 24K bytes of OTP (one time programming) ROM
T 256 bytes of RAM (which stores EDID for DDC1/2B)
T One 8-bit pre-loadable base timer
T 14 channels of 8 bit PWM outputs:
6 channel with 5V open drain and 8 channel with 12V
open drain
T 2 channel A/D converters with 6-bit resolution
T 24 bi-directional I/O port pins and 1 I/P pin
General Description
NT68P61A is a monitor component µC for auto-sync and
digital controlled applications. It contains a 6502
8-bit CPU core, 256 bytes of RAM used as working RAM
and stack area, 24K bytes of OTP ROM**, 14-channel 8-
bit PWM D/A converters, 2-channel A/D converters for
key detection saving I/O pins, one 8 bit pre-loadable
base timer, internal Hsync and Vsync signals processor
providing mode detection, watch-dog timer preventing
system from abnormal operation, and an I2C bus
interface. The LVRC enables NT68P61A operate
properly.
T Hsync/Vsync signal processor
T Hardware sync signals polarity & freq. evaluator
T Built-In I2C bus interface
T Supporting VESA DDC1/2B function
T Six-interrupt sources
- INTV (Vsync INT)
- INTE (External INT with rising edge trigger)
- INTMR (Timer INT )
- INTA (Slave Address Matched INT)
- INTD (Shift Register INT)
- INTS (SCL GO-LOW INT)
T Hardware watch-dog timer function
T Built-In Low Voltage reset circuit (LVRC)
Users can store EDID data in the 128 bytes of RAM for
DDC1/2B, so that users can save the cost of dedicated
EEPROM for EDID. Half frequency output function can
save external one-shot circuit. All of these designs create
savings in component costs.
* The frequency deviation of ceramic resonator has
+/- 6% maximum.
** The NT6861 (MASK ROM type) will provide
4/8/12/16/24K bytes program ROM.
1 V1.0
1 page  
NT68P61A
Functional Descriptions
1. 6502 CPU
The 6502 is an 8-bit CPU that provides 56 instructions, decimal and binary arithmetic, thirteen addressing modes, true
indexing capability, programmable stack pointer with variable length stack, a wide selection of addressable memory, and
interrupt input options.
The CPU clock cycle is 4MHz (8MHz system clock divided by 2). Refer to 6502 data sheet for more details.
7
Accumulator A
0
7
Index Register Y
0
7
Index Register X
0
15
Program Counter PCH
8
PCL
7
7
Stack Pointer SP
0
0
7
NV
0
B D I Z C Status Register P
Carry
Zero
IRQ Disable
Decimal Mode
BRK Command
Overflow
Negative
1 = TRUE
1 = Result ZERO
1 = DISABLE
1 = TRUE
1 = BRK
1 = TRUE
1 = NEG
Figure 1. 6502 CPU Registers and Status Flags
5
5 Page 
OTP ROM Mega Cell Timing Waveforms (PROGRAM Mode)
Tms
MODE DEC.
VPP
A0 - A14
TEST = VPP, MODE [0..2] = 000;
Tvs
Tas Tah
Tmh
CE
OE
DB0 - DB7
PGM
Tces
D IN
Tceh
Tdf
DOUT
Tdv
Tds Tpw Tdh
NT68P61A
11
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| Páginas | Total 48 Páginas | |
| PDF Descargar | [ Datasheet NT68P61A.PDF ] | |
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