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PDF NT6828 Data sheet ( Hoja de datos )
| Número de pieza | NT6828 | |
| Descripción | I2C Bus Controlled On-Screen Display | |
| Fabricantes | ETC | |
| Logotipo |  |
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NT6828
I2C Bus Controlled On-Screen Display
Features
T I2C Bus Interface with Slave Address $7A (Receiver
Only)
T Horizontal Frequency Range: 30KHz ~ 120KHz
T Flexible Display Resolution: up to 1524 dots per row
T Internal PLL Generating a Stable and Wide-Ranged
System Clock (92.2 MHz)
T OSD Screen Comprising of Character Arrays of 15
Rows by 30 Columns
T 12 X 18 Dot Matrix Per Character
T Total of 256 Fonts Including 248 ROM Fonts and 8
RAM Fonts
T Programmable Vertical and Horizontal Position
Adjustment for OSD Display Position
General Description
NT6828 is designed for displaying symbols and
characters onto a CRT monitor. Its operation is controlled
by the micro-controller with I2C bus interface. By sending
the proper data and commands to NT6828, it can carry
out the full screen display automatically while the time
base is generated by the on-chip PLL circuit. There are
many functions provided on this chip to fully support
numerous user applications. These functions are:
adjustment of OSD windows position, built-in ROM &
T 8-Color Selection for Each Character and 8-Color
Control on Each Row with Overlapped by Windows
T Character Blinking, Shadowing & Bordering Display
Effects
T Double Character Height and Width for Each Row
T Programmable Height of Characters Display
T Row To Row Spacing Control
T Four Overlapping and Programmable Windows with 8-
Color Control
T Hsync & Vsync Input Polarity Selectable
T 8 Channels PWM DAC with 8 bits resolution & Open-
Drain Output Structure
T 16 DIP and 24 Skinny DIP packages
RAM fonts, variable character height with row-to-row
spacing adjustment, 8 color selections for each character,
double height/width controls for each row, four available
overlapping windows with color & size controls, as well as
other I/O interfaces to compliment an external video
chipset.
NT6828 provides eight optional PWM channels with 8-bit
resolution for external digital to analog control.
Pin Configurations
AGND
VCO
RP
AVCC
HFLB
N.C.
SDA
SCL
16 DIP
1 16
2 15
3 14
4 13
5 12
6 11
7 10
89
DGND
R
G
B
FBKG
PWM/HFTON
VFLB
DVCC
AGND
VCO
RP
AV DD
HFLB
N.C.
SDA
SCL
PWM0
PWM1
PWM2
PWM3
24 Skinny DIP
1 24
2 23
3 22
4 21
5 20
6 19
7 18
8 17
9 16
10 15
11 14
12 13
DGND
R
G
B
FBKG
PWM/HFTON
VFLB
DVCC
PWM7
PWM6
PWM5
PWM4
1 V2.1
1 page  
NT6828
70
Window 1-4 Control Register
70
PWM Control Register
77
7
ROW
0
15 WINDOW1 - WINDOW4
0 11 12
COLUMN
7
0
OSD SCREEN
CONTROL
18 19
0
PWM CONTROL
0
OSD Screen Control Register
26
Memory Map of Control Register (Row 15)
5
5 Page 
NT6828
(5) OSD Screen Position Control Registers: Row 15, Column 12 - 13
Row 15
Column 12
7
MSB
6
5432
VPOS
Vertical Position Adjustment
10
LSB
Bit 7 - 0: VPOS - These bits determine the vertical starting position for the OSD screen display. It is the vertical delay
starting from the leading edge of VFLB. The unit of this setting is 4 horizontal lines.
The equation is defined as:
Vertical delay = (Vpos x 4 +1) x Horizontal Line
The default value of it is 4 ($04) after power on. Please refer Figure 5.
Row 15
Column 13
7
MSB
654321
HPOS
Horizontal Position Adjustment
0
LSB
Bit 7 - 0: HPOS- These bits determine the horizontal starting position for the OSD screen display. It is the horizontal
delay starting from the leading edge of HFLB. The unit of this setting is a 6-dot movement shift to the right on
the monitor screen. The equation is defined as:
Horizontal delay = (Hpos x 6 + 49) / P.R.
Where the P.R. (pixel rate) is defined by the HDR & Horizontal Frequency.
P.R. (Pixel Rate) = HDR * 12 * FreqHFLB
Please refer to the HDR control register at row15 / column15 for the P.R. setting.
After power-on, the default value of these bits is 15 ($ 0F). (Please refer to Figure 5.)
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet NT6828.PDF ] | |
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