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PDF MMDF2P02E Data sheet ( Hoja de datos )
| Número de pieza | MMDF2P02E | |
| Descripción | DUAL TMOS MOSFET 2.5 AMPERES 25 VOLTS | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MMDF2P02E/D
™Designer's Data Sheet
Medium Power Surface Mount Products
TMOS Dual P-Channel
Field Effect Transistors
MiniMOS™ devices are an advanced series of power MOSFETs
which utilize Motorola’s TMOS process. These miniature surface
mount MOSFETs feature ultra low RDS(on) and true logic level
performance. They are capable of withstanding high energy in the
avalanche and commutation modes and the drain–to–source diode
has a low reverse recovery time. MiniMOS devices are designed
for use in low voltage, high speed switching applications where
power efficiency is important. Typical applications are dc–dc
converters, and power management in portable and battery
powered products such as computers, printers, cellular and
cordless phones. They can also be used for low voltage motor
controls in mass storage products such as disk drives and tape
drives. The avalanche energy is specified to eliminate the
guesswork in designs where inductive loads are switched and offer
additional safety margin against unexpected voltage transients.
G
• Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life
• Logic Level Gate Drive — Can Be Driven by Logic ICs
• Miniature SO–8 Surface Mount Package — Saves Board Space
• Diode Is Characterized for Use In Bridge Circuits
• Diode Exhibits High Speed, with Soft Recovery
• IDSS Specified at Elevated Temperatures
• Avalanche Energy Specified
• Mounting Information for SO–8 Package Provided
MMDF2P02E
DUAL TMOS MOSFET
2.5 AMPERES
25 VOLTS
RDS(on) = 0.250 OHM
®
D
CASE 751–05, Style 11
SO–8
S
Source–1
18
Drain–1
Gate–1 2 7 Drain–1
Source–2 3 6 Drain–2
Gate–2 4 5 Drain–2
Top View
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)(1)
Rating
Symbol
Value
Unit
Drain–to–Source Voltage
Gate–to–Source Voltage — Continuous
Drain Current — Continuous @ TA = 25°C
Drain Current — Continuous @ TA = 100°C
Drain Current — Single Pulse (tp ≤ 10 µs)
Total Power Dissipation @ TA = 25°C (2)
Derate above 25°C
VDSS
VGS
ID
ID
IDM
PD
25 Vdc
± 20 Vdc
2.5 Adc
1.7
13 Apk
2.0 W
16 mW/°C
Operating and Storage Temperature Range
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 20 Vdc, VGS = 10 Vdc, Peak IL = 7.0 Apk, L = 10 mH, RG = 25 Ω)
Thermal Resistance, Junction to Ambient (2)
Maximum Lead Temperature for Soldering Purposes, 0.0625″ from case for 10 seconds
DEVICE MARKING
TJ, Tstg
EAS
RθJA
TL
– 55 to 150
245
62.5
260
°C
mJ
°C/W
°C
F2P02
(1) Negative sign for P–Channel device omitted for clarity.
(2) Mounted on 2” square FR4 board (1” sq. 2 oz. Cu 0.06” thick single sided) with one die operating, 10 sec. max.
ORDERING INFORMATION
Device
Reel Size
Tape Width
Quantity
MMDF2P02ER2
13″ 12 mm embossed tape
2500
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
Designer’s, E–FET and MiniMOS are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.
REV 5
©MMoottoororolal,aInTc.M19O9S6 Power MOSFET Transistor Device Data
1
1 page  
di/dt = 300 A/µs
Standard Cell Density
trr
High Cell Density
trr
ta tb
MMDF2P02E
t, TIME
Figure 11. Reverse Recovery Time (trr)
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain–to–source voltage and
drain current that a transistor can handle safely when it is for-
ward biased. Curves are based upon maximum peak junc-
tion temperature and a case temperature (TC) of 25°C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance – Gen-
eral Data and Its Use.”
Switching between the off–state and the on–state may tra-
verse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded, and that the transition
time (tr, tf) does not exceed 10 µs. In addition the total power
averaged over a complete switching cycle must not exceed
(TJ(MAX) – TC)/(RθJC).
A power MOSFET designated E–FET can be safely used
in switching circuits with unclamped inductive loads. For reli-
able operation, the stored energy from circuit inductance dis-
sipated in the transistor while in avalanche must be less than
the rated limit and must be adjusted for operating conditions
differing from those specified. Although industry practice is to
rate in terms of energy, avalanche energy capability is not a
constant. The energy rating decreases non–linearly with an
increase of peak current in avalanche and peak junction tem-
perature.
Although many E–FETs can withstand the stress of drain–
to–source avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous cur-
rent (ID), in accordance with industry custom. The energy rat-
ing must be derated for temperature as shown in the
accompanying graph (Figure 13). Maximum energy at cur-
rents below rated continuous ID can safely be assumed to
equal the values indicated.
100
VGS = 20 V
SINGLE PULSE
10 TC = 25°C
Mounted on 2” sq. FR4 board (1” sq. 2 oz. Cu 0.06”
thick single sided) with one die operating, 10s max.
100 µs 10 µs
10 ms
1 dc
0.1
0.01
0.1
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
1 10
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 12. Maximum Rated Forward Biased
Safe Operating Area
100
280
I pk = 7 A
240
200
160
120
80
40
0
25 50 75 100 125 150
TJ, STARTING JUNCTION TEMPERATURE (°C)
Figure 13. Maximum Avalanche Energy versus
Starting Junction Temperature
Motorola TMOS Power MOSFET Transistor Device Data
5
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet MMDF2P02E.PDF ] | |
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