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PDF MM74HCT573N Data sheet ( Hoja de datos )
| Número de pieza | MM74HCT573N | |
| Descripción | Octal D-Type Latch 3-STATE Octal D-Type Flip-Flop | |
| Fabricantes | Fairchild | |
| Logotipo |  |
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February 1990
Revised May 1999
MM74HCT573 • MM74HCT574
Octal D-Type Latch • 3-STATE Octal D-Type Flip-Flop
General Description
The MM74HCT573 octal D-type latches and
MM74HCT574 octal D-type flip-flop advanced silicon-gate
CMOS technology, which provides the inherent benefits of
low power consumption and wide power supply range, but
are LS-TTL input and output characteristic and pin-out
compatible. The 3-STATE outputs are capable of driving 15
LS-TTL loads. All inputs are protected from damage due to
static discharge by internal diodes to VCC and ground.
When the MM74HCT573 Latch Enable input is HIGH, the
Q outputs will follow the D inputs. When the Latch Enable
goes LOW, data at the D inputs will be retained at the out-
puts until Latch Enable returns HIGH again. When a high
logic level is applied to the Output Control input, all outputs
go to a high impedance state, regardless of what signals
are present at the other inputs and the state of the storage
elements.
The MM74HCT574 are positive edge triggered flip-flops.
Data at the D inputs, meeting the setup and hold time
requirements, are transferred to the Q outputs on positive
going transitions of the Clock (CK) input. When a high logic
level is applied to the Output Control (OC) input, all outputs
go to a high impedance state, regardless of what signals
are present at the other inputs and the state of the storage
elements.
The MM74HCT devices are intended to interface between
TTL and NMOS components and standard CMOS devices.
These parts are also plug in replacements for LS-TTL
devices and can be used to reduce power consumption in
existing designs.
Features
s TTL input characteristic compatible
s Typical propagation delay: 18 ns
s Low input current: 1 µA maximum
s Low quiescent current: 80 µA maximum
s Compatible with bus-oriented systems
s Output drive capability: 15 LS-TTL loads
Ordering Codes:
Order Number Package Number
Package Description
MM74HCT573WM
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
MM74HCT573SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HCT573MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HCT573N
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
MM74HCT574WM
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
MM74HCT574SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HCT574MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HCT574N
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
© 1999 Fairchild Semiconductor Corporation DS010627.prf
www.fairchildsemi.com
1 page  
AC Electrical Characteristics MM74HCT574
VCC = 5.0V, tr = tf = 6 ns, TA = 25°C
Symbol
Parameter
Conditions
fMAX
tPHL
tPLH
tPZH
tPZL
tPHZ
tPLZ
tW
tS
tH
Maximum Clock Frequency
Maximum Propagation Delay
to Output
Maximum Enable Propagation Delay
Control to Output
Maximum Disable Propagation Delay
Control to Output
Minimum Clock Pulse Width
Minimum Setup Time Data to Clock
Minimum Hold Time Clock to Data
CL = 45 pF
CL = 45 pF
RL = 1 kΩ
CL = 45 pF
RL = 1 kΩ
Typ
Guaranteed Limit
Units
60 33 MHz
17 27 ns
19 28 ns
14 25 ns
15 ns
12 ns
5 ns
AC Electrical Characteristics MM74HCT574
VCC = 5.0V ± 10%, tr = tf = 6 ns (unless otherwise specified)
Symbol
Parameter
Conditions
TA = 25°C TA = −40 to 85°C TA = −55 to 125°C Units
Typ Guaranteed Limits
fMAX
tPHL
tPLH
tPZH
tPZL
tPHZ
tPLZ
tTHL
tTLH
tW
tS
tH
CIN
COUT
CPD
Maximum Clock Frequency
Maximum Propagation Delay
Clock to Output
Maximum Enable Propagation
Delay Control to Output
Maximum Disable Propagation
Delay Control to Output
Maximum Output
Rise and Fall Time
Minimum Clock Pulse Width
Minimum Setup Time Data to Clock
Minimum Hold Time Clock to Data
Maximum Input Capacitance
Maximum Output Capacitance
Power Dissipation Capacitance
(Note 6)
CL = 50 pF
CL = 50 pF
RL = 1 kΩ
CL = 50 pF
RL = 1 kΩ
CL = 50 pF
OC = VCC
OC = GND
33
18 30
22 30
15 30
6 12
15
6 12
−1 5
10
20
5
58
28
38
38
38
15
20
15
6
10
20
23 MHz
45 ns
45 ns
45 ns
18 ns
24 ns
18 ns
8 ns
10 pF
20 pF
pF
Note 6: CPD determines the no load power consumption, PD = CPD VCC2 f + ICC VCC, and the no load dynamic current consumption, IS = CPD VCC f + ICC.
5 www.fairchildsemi.com
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| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet MM74HCT573N.PDF ] | |
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| MM74HCT573N | Octal D-Type Latch 3-STATE Octal D-Type Flip-Flop | Fairchild |
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