|
|
PDF MM74HCT374N Data sheet ( Hoja de datos )
| Número de pieza | MM74HCT374N | |
| Descripción | 3-STATE Octal D-Type Latch . 3-STATE Octal D-Type Flip-Flop | |
| Fabricantes | Fairchild | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de MM74HCT374N (archivo pdf) en la parte inferior de esta página. Total 9 Páginas | ||
|
No Preview Available !
February 1984
Revised February 1999
MM74HCT373 • MM74HCT374
3-STATE Octal D-Type Latch •
3-STATE Octal D-Type Flip-Flop
General Description
The MM74HCT373 octal D-type latches and
MM74HCT374 Octal D-type flip flops advanced silicon-
gate CMOS technology, which provides the inherent bene-
fits of low power consumption and wide power supply
range, but are LS-TTL input and output characteristic &
pin-out compatible. The 3-STATE outputs are capable of
driving 15 LS-TTL loads. All inputs are protected from dam-
age due to static discharge by internal diodes to VCC and
ground.
When the MM74HCT373 LATCH ENABLE input is HIGH,
the Q outputs will follow the D inputs. When the LATCH
ENABLE goes LOW, data at the D inputs will be retained at
the outputs until LATCH ENABLE returns HIGH again.
When a high logic level is applied to the OUTPUT CON-
TROL input, all outputs go to a high impedance state,
regardless of what signals are present at the other inputs
and the state of the storage elements.
The MM74HCT374 are positive edge triggered flip-flops.
Data at the D inputs, meeting the setup and hold time
requirements, are transferred to the Q outputs on positive
going transitions of the CLOCK (CK) input. When a high
logic level is applied to the OUTPUT CONTROL (OC)
input, all outputs go to a high impedance state, regardless
of what signals are present at the other inputs and the state
of the storage elements.
MM74HCT devices are intended to interface between TTL
and NMOS components and standard CMOS devices.
These parts are also plug in replacements for LS-TTL
devices and can be used to reduce power consumption in
existing designs.
Features
s TTL input characteristic compatible
s Typical propagation delay: 20 ns
s Low input current: 1 µA maximum
s Low quiescent current: 80 µA maximum
s Compatible with bus-oriented systems
s Output drive capability: 15 LS-TTL loads
Ordering Code:
Order Number Package Number
Package Descriptions
MM74HCT373WM
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
MM74HCT373SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HCT373MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HCT373N
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
MM74HCT373WM
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
MM74HCT373SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HCT373MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HCT373N
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
© 1999 Fairchild Semiconductor Corporation DS005367.prf
www.fairchildsemi.com
1 page  
AC Electrical Characteristics
MM74HCT373: VCC = 5.0V, tr = tf = 6 ns TA = 25°C (unless otherwise specified)
Symbol
Parameter
Conditions
tPHL, tPLH
tPHL, tPLH
tPZH, tPZL
tPHZ, tPLZ
tW
tS
tH
Maximum Propagation Delay
Data to Output
Maximum Propagation Delay
Latch Enable to Output
Maximum Enable Propagation Delay
Control to Output
Maximum Disable Propagation Delay
Control to Output
Minimum Clock Pulse Width
Minimum Setup Time Data to Clock
Minimum Hold Time Clock to Data
CL = 45 pF
CL = 45 pF
CL = 45 pF
RL = 1 kΩ
CL = 5 pF
RL = 1 kΩ
Guaranteed
Typ Units
Limit
18 25 ns
21 30 ns
20 28 ns
18 25 ns
16 ns
5 ns
10 ns
AC Electrical Characteristics
MM74HCT373: VCC = 5.0V ± 10%, tr = tf = 6 ns (unless otherwise specified)
Symbol
Parameter
Conditions
TA=25°C
Typ
TA=−40 to 85°C TA=−55 to 125°C
Guaranteed Limits
tPHL, tPLH Maximum Propagation
Delay Data to Output
tPHL, tPLH Maximum Propagation Delay
Latch Enable to Output
tPZH, tPZL Maximum Enable Propagation
Delay Control to Output
tPHZ, tPLZ Maximum Disable Propagation
Delay Control to Output
tTHL, tTLH Maximum Output Rise
and Fall Time
CL = 50 pF
CL = 150 pF
CL = 50 pF
CL = 150 pF
CL = 50 pF
CL = 150 pF
RL = 1 kΩ
CL = 50 pF
RL = 1 kΩ
CL = 50 pF
22 30
30 40
25 35
32 45
21 30
30 40
21 30
8 12
37
50
44
56
37
50
37
15
45
60
53
68
45
60
45
18
tW
tS
tH
CIN
COUT
CPD
Minimum Clock Pulse Width
Minimum Setup Time Data to Clock
Minimum Hold Time Clock to Data
Maximum Input Capacitance
Maximum Output Capacitance
Power Dissipation Capacitance
(Note 5)
OC = VCC
OC = GND
16 20
56
10 13
10 10
20 20
5
52
24
8
20
10
20
Note 5: CPD determines the no load dynamic power consumption, PD = CPD VCC2 f + ICC VCC, and the no load dynamic current consumption,
IS = CPD VCC f + ICC.
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
pF
pF
pF
5 www.fairchildsemi.com
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet MM74HCT374N.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| MM74HCT374 | 3-STATE Octal D-Type Latch . 3-STATE Octal D-Type Flip-Flop | Fairchild |
| MM74HCT374 | Octal Flip-Flop |  National Semiconductor |
| MM74HCT374MTC | 3-STATE Octal D-Type Latch . 3-STATE Octal D-Type Flip-Flop | Fairchild |
| MM74HCT374N | 3-STATE Octal D-Type Latch . 3-STATE Octal D-Type Flip-Flop | Fairchild |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |