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PDF MM74HCT32 Data sheet ( Hoja de datos )
| Número de pieza | MM74HCT32 | |
| Descripción | Quad 2-Input OR Gate | |
| Fabricantes | Fairchild | |
| Logotipo |  |
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MM74HCT32
Quad 2-Input OR Gate
Features
■ TTL, LS pin-out and threshold compatible
■ Fast switching: tPLH, tPHL = 10ns (typ.)
■ Low power: 10µW at DC
■ High fan-out, 10 LS-TTL loads
February 2008
General Description
The MM74HCT32 is a logic function fabricated by using
advanced silicon-gate CMOS technology, which pro-
vides the inherent benefits of CMOS—low quiescent
power and wide power supply range. This device is input
and output characteristic and pin-out compatible with
standard 74LS logic families. All inputs are protected
from static discharge damage by internal diodes to VCC
and ground.
MM74HCT devices are intended to interface between
TTL and NMOS components and standard CMOS
devices. These parts are also plug-in replacements for
LS-TTL devices and can be used to reduce power
consumption in existing designs.
Ordering Information
Order Number
MM74HCT32M
MM74HCT32SJ
MM74HCT32MTC
MM74HCT32N
Package
Number
M14A
M14D
MTC14
N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150"
Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,
4.4mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
©1987 Fairchild Semiconductor Corporation
MM74HCT32 Rev. 1.3.0
www.fairchildsemi.com
1 page  
Physical Dimensions
8.75
8.50
7.62
14
6.00
A
8
B
4.00
3.80
0.65
5.60
PIN ONE
INDICATOR
1
1.27
(0.33)
7
0.51
0.35
1.70
1.27
LAND PATTERN RECOMMENDATION
0.25 M C B A
1.75 MAX
1.50
1.25
R0.10
R0.10
8°
0°
SEE DETAIL A
0.25
0.10 C
0.10 C
0.25
0.19
NOTES: UNLESS OTHERWISE SPECIFIED
0.50
0.25
A) THIS PACKAGE CONFORMS TO JEDEC
X 45°
MS-012, VARIATION AB, ISSUE C,
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
GAGE PLANE FLASH OR BURRS.
D) LANDPATTERN STANDARD:
0.36
SOIC127P600X145-14M
E) DRAWING CONFORMS TO ASME Y14.5M-1994
F) DRAWING FILE NAME: M14AREV13
0.90
0.50
(1.04)
SEATING PLANE
DETAIL A
SCALE: 20:1
Figure 1. 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©1987 Fairchild Semiconductor Corporation
MM74HCT32 Rev. 1.3.0
5
www.fairchildsemi.com
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet MM74HCT32.PDF ] | |
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