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PDF MM74C574SJ Data sheet ( Hoja de datos )
| Número de pieza | MM74C574SJ | |
| Descripción | 3-STATE Octal D-Type Edge-Triggered Flip-Flop | |
| Fabricantes | Fairchild | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de MM74C574SJ (archivo pdf) en la parte inferior de esta página. Total 7 Páginas | ||
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September 1983
Revised February 1999
MM74HC574
3-STATE Octal D-Type Edge-Triggered Flip-Flop
General Description
The MM74HC574 high speed octal D-type flip-flops utilize
advanced silicon-gate P-well CMOS technology. They pos-
sess the high noise immunity and low power consumption
of standard CMOS integrated circuits, as well as the ability
to drive 15 LS-TTL loads. Due to the large output drive
capability and the 3-STATE feature, these devices are ide-
ally suited for interfacing with bus lines in a bus organized
system.
These devices are positive edge triggered flip-flops. Data
at the D inputs, meeting the set-up and hold time require-
ments, are transferred to the Q outputs on positive going
transitions of the CLOCK (CK) input. When a high logic
level is applied to the OUTPUT CONTROL (OC) input, all
outputs go to a high impedance state, regardless of what
signals are present at the other inputs and the state of the
storage elements.
The 74HC logic family is speed, function, and pinout com-
patible with the standard 74LS logic family. All inputs are
protected from damage due to static discharge by internal
diode clamps to VCC and ground.
Features
s Typical propagation delay: 18 ns
s Wide operating voltage range: 2V–6V
s Low input current: 1 µA maximum
s Low quiescent current: 80 µA maximum
s Compatible with bus-oriented systems
s Output drive capability: 15 LS-TTL loads
Ordering Code:
Order Number Package Number
Package Description
MM74C574WM
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300”
MM74C574SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74C574MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4m Wide
MM74C574N
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Truth Table
Pin Assignments for DIP, SOIC, SOP and TSSOP
Output
Control
L
L
L
H
Clock
↑
↑
L
X
Data
H
L
X
X
Output
H
L
Q0
Z
H = HIGH Level
L = LOW Level
X = Don't Care
↑ = Transition from LOW-to-HIGH
Z = High Impedance State
Q0 = The level of the output before steady state input conditions were
established
Top View
© 1999 Fairchild Semiconductor Corporation DS005213.prf
www.fairchildsemi.com
1 page  
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
Package Number M20B
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
5
www.fairchildsemi.com
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| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet MM74C574SJ.PDF ] | |
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