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PDF ML4800 Data sheet ( Hoja de datos )
| Número de pieza | ML4800 | |
| Descripción | Power Factor Correction and PWM Controller Combo | |
| Fabricantes | Fairchild | |
| Logotipo |  |
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March 2001
PRELIMINARY
ML4800
Power Factor Correction and PWM Controller Combo
GENERAL DESCRIPTION
FEATURES
The ML4800 is a controller for power factor corrected,
switched mode power supplies. Power Factor Correction
(PFC) allows the use of smaller, lower cost bulk capacitors,
reduces power line loading and stress on the switching
FETs, and results in a power supply that fully complies
with IEC1000-3-2 specification. Intended as a BiCMOS
version of the industry-standard ML4824, the ML4800
includes circuits for the implementation of leading edge,
average current, “boost” type power factor correction and
a trailing edge, pulse width modulator (PWM). It also
includes a TriFault Detect™ function to help ensure that no
unsafe conditions will result from single component failure
in the PFC. Gate-drivers with 1A capabilities minimize the
need for external driver circuits. Low power requirements
improve efficiency and reduce component costs.
An over-voltage comparator shuts down the PFC section in
the event of a sudden decrease in load. The PFC section
also includes peak current limiting and input voltage
brownout protection. The PWM section can be operated in
current or voltage mode, at up to 250kHz, and includes an
accurate 50% duty cycle limit to prevent transformer
saturation.
I Internally synchronized leading-edge PFC and trailing-
edge PWM in one IC
I TriFault Detect™ for UL1950 compliance and
enhanced safety
I Slew rate enhanced transconductance error amplifier
for ultra-fast PFC response
I Low power: 200µA startup current, 5.5mA operating
current
I Low total harmonic distortion, high PF
I Reduced ripple current in storage capacitor between
PFC and PWM sections
I Average current, continuous boost leading edge PFC
I PWM configurable for current-mode or voltage mode
operation
I Current fed gain modulator for improved noise immunity
I Overvoltage and brown-out protection, UVLO, and soft
start
BLOCK DIAGRAM
16
VEAO
1
IEAO
VFB
15
2.5V
IAC
2
VRMS
4
ISENSE
3
VEA
-
+
1.6kΩ IEA
+
-
GAIN
MODULATOR
1.6kΩ
POWER FACTOR CORRECTOR
0.5V
+
TRI-FAULT
+
- 2.75V
OVP
+
-
- -1V +
-
PFC ILIMIT
RAMP 1
7
OSCILLATOR
RAMP 2
8
DUTY CYCLE
LIMIT
VCC
17V
13
VCC
7.5V
REFERENCE
VREF
14
SQ
RQ
SQ
PFC OUT
12
RQ
VDC
6
VCC
SS
5
25µA
1.25V
DC ILIMIT VREF
9
-
+
-
+
VFB
2.45V
VIN OK
-
+
1.0V
-
+ DC ILIMIT
PULSE WIDTH MODULATOR
VCC
SQ
RQ
PWM OUT
11
UVLO
REV. 1.0.2 3/7/2001
1 page  
ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
REFERENCE
Output Voltage
Line Regulation
Load Regulation
Temperature Stability
Total Variation
Long Term Stability
PFC
Minimum Duty Cycle
Maximum Duty Cycle
Output Low Voltage
Output High Voltage
PWM
Rise/Fall Time
Duty Cycle Range
Output Low Voltage
Output High Voltage
SUPPLY
Rise/Fall Time
Start-up Current
Operating Current
Undervoltage Lockout Threshold
Undervoltage Lockout Hysteresis
CONDITIONS
TA = 25°C, I(VREF) = 1mA
11V <VCC <16.5V
0mA <I(VREF) <10mA;
TA = 0ºC to 70ºC
0mA < I(VREF) < 5mA;
TA = –40ºC to 85ºC
Line, Load, Temp
TJ = 125°C, 1000 Hours
VIEAO > 4.0V
VIEAO < 1.2V
IOUT = -20mA
IOUT = -100mA
IOUT = 10mA, VCC = 9V
IOUT = 20mA
IOUT = 100mA
CL = 1000pF
IOUT = -20mA
IOUT = -100mA
IOUT = 10mA, VCC = 9V
IOUT = 20mA
IOUT = 100mA
CL = 1000pF
VCC = 12V, CL = 0
14V, CL = 0
Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions.
Note 2: Includes all bias currents to other circuits connected to the VFB pin.
Note 3: Gain = K x 5.3V; K = (IGAINMOD - IOFFSET) x [IAC (VEAO - 0.625)]-1; VEAOMAX=5V.
ML4800
MIN TYP MAX UNITS
7.4 7.5 7.6 V
10 25 mV
10 20 mV
10 20 mV
0.4 %
7.35
7.65
V
5 25 mV
0%
90 95
%
0.4 0.8 V
0.7 2.0 V
0.4 0.8 V
VCC – 0.8V
VCC - 2V
50
V
V
ns
0-44
0-47
0.4
0.7
0.4
VCC – 0.8V
VCC - 2V
50
0-49
0.8
2.0
0.8
%
V
V
V
V
V
ns
200 350 µA
5.5 7 mA
12.4 13 13.6 V
2.5 2.8 3.1 V
REV. 1.0.2 3/7/2001
5
5 Page 
FUNCTIONAL DESCRIPTION (Continued)
CSS
=
t DELAY
×
25µA
1.25V
where CSS is the required soft start capacitance, and
tDELAY is the desired start-up delay.
(6)
It is important that the time constant of the PWM soft-start
allow the PFC time to generate sufficient output power for
the PWM section. The PWM start-up delay should be at
least 5ms.
Solving for the minimum value of CSS:
CSS
=
5ms
×
25µA
1.25V
= 100nF
(6a)
Caution should be exercised when using this minimum
soft start capacitance value because premature charging of
the SS capacitor and activation of the PWM section can
result if VFB is in the hysteresis band of the VIN OK
comparator at start-up. The magnitude of VFB at start-up is
related both to line voltage and nominal PFC output
voltage. Typically, a 1.0µF soft start capacitor will allow
time for VFB and PFC out to reach their nominal values
prior to activation of the PWM section at line voltages
between 90Vrms and 265Vrms.
Generating VCC
The ML4800 is a voltage-fed part. It requires an external
15V, ±10% (or better) shunt voltage regulator, or some
other VCC regulator, to regulate the voltage supplied to the
part at 15V nominal. This allows low power dissipation
ML4800
while at the same time delivering 13V nominal gate drive
at the PWM OUT and PFC OUT outputs. If using a Zener
diode for this function, it is important to limit the current
through the Zener to avoid overheating or destroying it.
This can be easily done with a single resistor in series with
the Vcc pin, returned to a bias supply of typically 18V to
20V. The resistor’s value must be chosen to meet the
operating current requirement of the ML4800 itself
(8.5mA, max.) plus the current required by the two gate
driver outputs.
EXAMPLE:
With a VBIAS of 20V, a VCC of 15V and the ML4800 driving
a total gate charge of 90nC at 100kHz (e.g., 1 IRF840
MOSFET and 2 IRF820 MOSFETs), the gate driver current
required is:
IGATEDRIVE = 100kHz × 90nC = 9mA
RBIAS
=
VBIAS − VCC
ICC + IG + Iz
(7)
(8)
RBIAS
=
20V−15V
6mA+9mA+5mA
=250Ω
Choose RBIAS = 240Ω.
The ML4800 should be locally bypassed with a 1.0µF
ceramic capacitor. In most applications, an electrolytic
capacitor of between 47µF and 220µF is also required
across the part, both for filtering and as part of the start-up
bootstrap circuitry.
L1
I1
+
VIN
DC
SW2 I2 I3
I4
SW1
C1
RL
REF +–EAU3
RAMP
OSC
CLK
U4
+
– U1
DFF
RQ
D U2
Q
CLK
RAMP
VEAO
VSW1
TIME
Figure 4. Typical Trailing Edge Control Scheme
TIME
REV. 1.0.2 3/7/2001
11
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet ML4800.PDF ] | |
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