|
|
PDF MK50H25 Data sheet ( Hoja de datos )
| Número de pieza | MK50H25 | |
| Descripción | HIGH SPEED LINK LEVEL CONTROLLER | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de MK50H25 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
SECTION 1 - FEATURES
System clock rate up to 33 MHz (MK50H25 -
33), 25 MHz (MK50H25 - 25), or 16 MHz
(MK50H25 - 16).
Data rate up to 20 Mbps continuous
(MK50H25 - 33) or up to 51 Mbps bursted
On chip DMA control with programmable burst
length.
DMA transfer rate of up to 13.3 Mbytes/sec us-
ing optional 5 SYSCLK DMA cycle (150 nS) at
33 MHz SYSCLK.
Complete Level 2 implementation compatible
with X.25 LAPB, ISDN LAPD, X.32, and X.75
Protocols.
Handles all error recovery, sequencing, and S
and U frame control.
Pin-for-pin and architecturally compatible with
MK5025 (X.25/LAPD), MK5027 (CCS#7) and
MK5029(SDLC).
Buffer Management includes:
- Initialization Block
- Separate Receive and Transmit Rings
- Variable Descriptor Ring and Window Sizes.
Separate 64-byte Transmit and Receive FIFO.
Programmable Transmit FIFO hold-off water-
mark.
Handles all HDLC frame formatting:
- Zero bit insertion and deletion
- FCS (CRC) generation and detection
- Frame delimiting with flags
Programmable Single or Extended Address
and Control fields.
Five programmable timer/counters: T1, T3,
TP, N1, N2
Programmable minimum frame spacing on
transmission (number of flags between
frames).
- Programmable from 1 to 62 flags between
frames
Selectable FCS (CRC) of 16 or 32 bits, and
passing of entire FCS to buffer.
Testing Facilities:
- Internal Loopback
- Silent Loopback
- Optional Internal Data Clock Generation
- Self Test.
Programmable for full or half duplex operation
July 1994
MK50H25
HIGH SPEED
LINK LEVEL CONTROLLER
ADVANCE DATA
DIP48
PLCC 52
Programmable Watchdog Timers for RCLK
and TCLK (to detect absence of data clocks)
Option causing received data to effectively be
odd-byte aligned, in addition to standard even-
byte alignment.
Available in 52 pin PLCC, 84 pin PLCC(for use
with external ROM), or 48 pin DIP packages.
SECTION 2 - INTRODUCTION
The SGS - Thomson MK502H5 Link Level Con-
troller is a VLSI semiconductor device which pro-
vides complete link level data communications
control conforming to the 1984 and 1988 CCITT
versions of X.25. The MK50H25 will perform
frame formating including: frame delimiting with
flags, transparency (so-called ”bit-stuffing”), error
recovery by retransmission, sequence number
control, S (supervisory) and U (unnumbered)
frame control, plus FCS (CRC) generation and
detection. The MK50H25 also supports X.75 and
X.32 (with its XID frame support), as well as sin-
gle channel ISDN LAPD (with its support of UI
frames and extended addressing capabilities).
1/64
1 page  
MK50H25
Table 1: PIN DESCRIPTION (continued)
SIGNAL NAME PIN(S)
HOLD
B USRQ
17
[19]
ALE 18
AS [20]
HLDA
CS
ADR
19
[21]
20
[22]
21
[23]
READY
22
[24]
TYPE
IO/OD
O/3S
I
I
I
IO/OD
DESCRIPTION
If CSR4<00> BCON = 1,
I/O PIN 15 = BYTE (O/3S)
I/O PIN 16 = BUSAKO(O)
Byte selection is done using the BYTE line and DAL<00> latched during the
address portion of the bus transaction. MK50H25 drives BYTE only as a Bus
Master and ignores it when a Bus Slave. Byte selection is done as outlined
in the following table.
BYTE
DAL<00> TYPE OF TRANSFER
LOW
LOW
ENTIRE WORD
LOW
HIGH
ILLEGAL CONDITION
HIGH
LOW
LOWER BYTE
HIGH
HIGH
UPPER BYTE
BUSAKO is a bus request daisy chain output. If MK50H25 is not requesting
the bus and it receives HLDA, BUSAKO will be driven low. If MK50H25 is
requesting the bus when it receives HLDA, BUSAKO will remain high
Note: All transfers are entire word unless the MK50H25 is configured for 8 bit
operation.
Pin 17 is configured through bit 0 of CSR4.
If CSR4<00> BCON = 0,
I/O PIN 17 = HOLD
HOLD request is asserted by MK50H25 when it requires a DMA cycle, if
HLDA is inactive, regardless of the previous state of the HOLD pin. HOLD is
held low for the entire ensuing bus transaction.
If CSR4<00> BCON = 1,
I/O PIN 17 = BUSRQ
BUSRQ is asserted by MK50H25 when it requires a DMA cycle if the prior
state of the BUSRQ pin was high and HLDA is inactive. BUSRQ is held low
for the entire ensuing bus transaction.
The active level of ADDRESS STROBE is programmable through CSR4.
The address portion of a bus transfer occurs while this signal is at its
asserted level. This signal is driven by MK50H25 while it is the BUS
MASTER. At all other times, the signal is tristated.
If CSR4<01> ACON = 0,
I/O PIN 18 = ALE
ADDRESS LATCH ENABLE is used to demultiplex the DAL lines and define
the address portion of the transfer. As ALE, the signal transitions from high
to low during the address portion of the transfer and remains low during the
data portion.
If CSR4<01> ACON = 1,
I/O PIN 18 = AS
As AS, the signal pulses low during the address portion of the bus transfer.
The low to high transition of AS can be used by a slave device to strobe the
address into a register.
AS is effectively the inversion of ALE.
HOLD ACKNOWLEDGE is the response to HOLD. When HLDA is low in
response to MK50H25’s assertion of HOLD, the MK50H25 is the Bus
Master. HLDA should be deasserted ONLY after HOLD has been released
by the MK50H25.
CHIP SELECT indicates, when low, that the MK50H25 is the slave device
for the data transfer. CS must be valid throughout the entire transaction.
ADDRESS selects the Register Address Port or the Register Data Port. It
must be valid throughout the data portion of the transfer and is only used by
the chip when CS is low.
ADR
PORT
LOW
REGISTER DATA PORT
HIGH
REGISTER ADDRESS PORT
When the MK50H25 is a Bus Master, READY is an asynchronous
acknowledgement from the bus memory that memory will accept data in a
WRITE cycle or that memory has put data on the DAL lines in a READ cycle.
5/64
5 Page 
scriptor ring in a ”look ahead” manner. If the
frame is too long for one buffer, the next buffer
will be used after filling the first buffer; that is,
”chained”. The MK50H25 will then ”look ahead”
to the next buffer, and chain that buffer if neces-
sary, and so on.The operational parameters for
the buffer management are defined by the user in
the initialization block. The parameters defined
include the basic mode of operation, the number
of entries for the transmitter and receiver descrip-
tor rings, frame Address field, etc. The starting
address for the Initialization block, IADR, is de-
fined in the CSR2 and CSR3 registers inside the
MK50H25.
3.2.3 Frame Format
The frame format supported by the MK50H25 is
shown below. Each frame may consist of a pro-
grammable number of leading flag patterns
(01111110), an address field, a control field, an
information field, an FCS (CRC) of either 16 or 32
bits, and a trailing flag pattern. The number of
leading flags transmitted is programmable
through the Mode Register in the Initialization
Block. Received frames may have as few as one
flag between adjacent frames
TRANSMITTED FIRST
F AC
8 8/16 8/16
INFO
8*n
FCS
16/32
F
8
MK50H25
3.2.4 The Command/Response Repertoire
The command/response repertoire of the
MK50H25 is shown in Tables A and B. This set
conforms to the 1984 & 1988 CCITT X.25, plus
support of XID, Test, and UI frames conforming to
ISDN LAPD. The MK50H25 will process the In-
formation, Supervisory, and Unnumbered frames
shown in Tables A and B, and will handle the A
and C fields for all I and UI frames.
The symbols and definitions for the frame types
are:
Name
I
UI
RR
RNR
REJ
FRMR
UA
SABM
DISC
DM
TEST
XID
Definition
Information frame
Unnumbered Information frame
Receiver Ready
Receiver Not Ready
Reject
Frame Reject
Unnumbered Acknowledge
Set Asynchronous Balance Mode
Disconnect
Disconnect Mode
Link Test Frame
Exchange Identification
11/64
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MK50H25.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| MK50H25 | HIGH SPEED LINK LEVEL CONTROLLER | ST Microelectronics |
| MK50H27 | Signalling System 7 Link Controller | ST Microelectronics |
| MK50H28 | MULTI LOGICAL LINK FRAME RELAY CONTROLLER | ST Microelectronics |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |