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PDF MK2771-16 Data sheet ( Hoja de datos )
| Número de pieza | MK2771-16 | |
| Descripción | VCXO and Set-Top Clock Source | |
| Fabricantes | Integrated Circuit Systems | |
| Logotipo |  |
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I CR O C LOC K
Description
The MK2771-16 is a low cost, low jitter, high
performance VCXO and clock synthesizer
designed for set-top boxes. The on-chip Voltage
Controlled Crystal Oscillator accepts a 0 to 3V
input voltage to cause the output clocks to vary by
±100 ppm. Using ICS/MicroClock’s patented
VCXO and analog Phase-Locked Loop (PLL)
techniques, the device uses an inexpensive
13.5 MHz crystal input to produce multiple
output clocks including a selectable processor
clock, a selectable audio clock, two
communications clocks, a 13.5 MHz clock, and
three 27 MHz clocks. All clocks are frequency
locked to the 27.00MHz output (and to each
other) with zero ppm error, so any output can be
used as the VCXO output.
MK2771-16
VCXO and Set-Top Clock Source
Features
• Packaged in 28 pin SSOP (QSOP)
• On-chip patented VCXO with pull range
of 200ppm (minimum)
• VCXO tuning voltage of 0 to 3V
• Processor frequency include 16.66, 20, 25, 32, 40,
and 50 MHz
• Audio clocks support 32 kHz, 44.1 kHz, 48 kHz
and 96 kHz sampling rates
• Zero ppm synthesis error in all clocks (all exactly
track 27MHz VCXO)
• Uses an inexpensive 13.5 MHz crystal
• Full CMOS output swings with 25mA output
drive capability at TTL levels
• Advanced, low power, sub-micron CMOS process
• 5V operating voltage with 3.3V capable I/O
Block Diagram
VDD5 GND VDDIO
AS2:0
PS1, PS0
CS1, CS0
VIN
13.5 MHz X1
pullable
crystal
X2
3
2
2
Voltage
Controlled
Crystal
Oscillator
PLL
Clock
Synthesis
Circuitry
x2
PLL
÷2
Output
Buffer
Output
Buffer
ACLK
PCLK
Output
Buffer
CCLK1
Output
Buffer
CCLK2
Output
Buffers
3
27.000 MHz
Output
Buffer
13.500 MHz
MDS 2771-16 C
1
Revision 102099
Printed 11/16/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA •95126•(408) 295-9800tel• www.icst.com
1 page | ||
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| PDF Descargar | [ Datasheet MK2771-16.PDF ] | |
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