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PDF MB15C03PFV Data sheet ( Hoja de datos )
| Número de pieza | MB15C03PFV | |
| Descripción | Single Serial Input PLL Frequency Synthesizer On-Chip prescaler | |
| Fabricantes | Fujitsu | |
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FUJITSU SEMICONDUCTOR
DATA SHEET
DS04-21349-1E
ASSP
Single Serial Input
PLL Frequency Synthesizer
On-Chip prescaler
MB15C03
s DESCRIPTION
The Fujitsu MB15C03 is a serial input Phase Locked Loop (PLL) frequency synthesizer with a prescaler. A 64/
65 division is available for the prescaler that enables pulse swallow operation.
This operates with a supply voltage of 1.0 V (min.).
MB15C03 is suitable for mobile communications, such as paging systems.
s FEATURES
• Frequency operation
90 MHz @VDD = 1.0 to 1.5V
120 MHz @VDD = 1.2 to 1.5V
• Separate power supply : VDD = 1.0 to 1.5 V (for overall system)
VP = 2.0V to 3.5V (for a charge pump)
• Power saving function
• Pulse swallow function: 64/65
• Serial input 14-bit programmable reference divider: R = 5 to 16,383
• Serial input 18-bit programmable divider consisting of:
- Binary 6-bit swallow counter: 0 to 63
- Binary 12-bit programmable counter: 5 to 4,095
• Wide operating temperature: Ta = –20 to +60°C
• Plastic 16-pin SSOP package (FPT-16P-M05)
s PACKAGE
16-pin, plastic SSOP
(FPT-16P-M05)
This device contains circuitry to protect the inputs against damage due to high static voltages or electroc fields. However, it is advised that normal precautions
be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit.
1 page  
MB15C03
s ABSOLUTE MAXIMUM RATINGS
Parameter
Power supply voltage
Input voltage
Output voltage
Output current
Operating temperature
Storage temperature
Symbol
VDD
VP
VIN
VOUT
VOUTP
IOUT
Ta
Tstg
Rating
Min.
Max.
GND –0.5
+2.0
GND –0.5
+5.0
GND –0.5
VDD +0.5
GND –0.5
VDD +0.5
GND –0.5
VP +0.5
–10 +10
–20 +60
–40 +125
Unit
Remark
V
V
V
V
V
mA
°C
°C
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
s RECOMMENDED OPERATING CONDITIONS
Parameter
Power supply voltage
Input voltage
Operating temperature
Symbol
VDD
VP
VIN
Ta
Min.
1.0
1.2
2.0
GND
–20
Value
Typ.
—
—
—
—
—
Max.
1.5
1.5
3.5
VDD
+60
Unit
Remark
V
For 90 MHz
For 120 MHz
V
V
°C
WARNING:
Recommended operating conditions are normal operating ranges for the semiconductor device. All
the device’s electrical characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside
these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representative beforehand.
HandIing Precautions
• This device should be transported and stores in anti-static containers.
• This is a static-sensitive device; take proper anti-ESD precautions. Ensure that personnel and equipment are
properly grounded. Cover workbenches with grounded conductive mats.
• Always turn the power supply off before inserting or removing the device from its socket.
• Protect leads with a conductive sheet when handling or transporting PC boards with devices.
5
5 Page 
MB15C03
3. Setting the Divide Ratio
(1) Serial data format
The format of the serial data is shown is Figure 3. The serial data is composed of control bits and divide ratio
setting data. The contorl bits select the programmable divider or programmable reference divider.
In case of the programmable divider, serial data consists of 18 bits (6 bits for the swallow counter and 12 bits
for the programmable counter) and control bits as shown in Figure 3.1. In case of the programmable reference
divider, the serial data consists of 14 bits and 2 control bits as shown in Figure 3.2.
The control bits are set to:
C0 = C1= 0
for the programmable divider
C0 = 0, C1 = 1 for the programmable reference divider.
Figure 3 Serial data format
LSB
Direction of data input
MSB
CCAAAAAANNNNNNNNNNNN
0 1 0 1 2 3 4 5 0 1 2 3 4 5 6 7 8 9 10 11
(=0) (=0)
Swallow counter
Programmable counter
Control bit
Figure 3.1 Divide ratio for the programmable divider
LSB
Direction of data input
MSB
CCRRRRRRRRRRRRRR
0 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13
(=0) (=1)
Programmable reference counter
Control bit
Figure 3.2 Divide ratio for the programmable reference divider
(2) The flow of serial data
Serial data is received via data pin in synchronization with the clock input and loaded into shift register which
contains the divide ratio setting data and into the control register which contains the control bit. The logical
product (through the AND gate in Figure 4) of LE and the control register output (i.e., control bit) is fed to the
enable input of the latches. Accordingly, when LE is set high, the latch for the divider identitied by the control bit
is enabled and the divide ratio data from the shift register is loaded into the selected counter(s).
11
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet MB15C03PFV.PDF ] | |
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